Blackfin: uart: fix printf warning

[karo-tx-uboot.git] / README

diff --git a/README b/README
index 68ef2b2e9988b936d0ab76df086febf64a47b59d..1e2d4d33c0665972e0a881a9a10a53eccc63548f 100644 (file)
--- a/README
+++ b/README
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000 - 2009
+# (C) Copyright 2000 - 2011
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -363,6 +363,11 @@ The following options need to be configured:
                system clock.  On most PQ3 devices this is 8, on newer QorIQ
                devices it can be 16 or 32.  The ratio varies from SoC to Soc.
 
+               CONFIG_SYS_FSL_PCIE_COMPAT
+
+               Defines the string to utilize when trying to match PCIe device
+               tree nodes for the given platform.
+
 - Intel Monahans options:
                CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -455,6 +460,17 @@ The following options need to be configured:
                Note: If a "bootargs" environment is defined, it will overwride
                the defaults discussed just above.
 
+- Cache Configuration:
+               CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
+               CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
+               CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
+
+- Cache Configuration for ARM:
+               CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
+                                     controller
+               CONFIG_SYS_PL310_BASE - Physical base address of PL310
+                                       controller register space
+
 - Serial Ports:
                CONFIG_PL010_SERIAL
 
@@ -709,8 +725,8 @@ The following options need to be configured:
                                          (requires CONFIG_CMD_MEMORY)
                CONFIG_CMD_SOURCE         "source" command Support
                CONFIG_CMD_SPI          * SPI serial bus support
+               CONFIG_CMD_TFTPSRV      * TFTP transfer in server mode
                CONFIG_CMD_USB          * USB support
-               CONFIG_CMD_VFD          * VFD support (TRAB)
                CONFIG_CMD_CDP          * Cisco Discover Protocol support
                CONFIG_CMD_FSL          * Microblaze FSL support
 
@@ -739,10 +755,17 @@ The following options need to be configured:
 - Watchdog:
                CONFIG_WATCHDOG
                If this variable is defined, it enables watchdog
-               support. There must be support in the platform specific
-               code for a watchdog. For the 8xx and 8260 CPUs, the
-               SIU Watchdog feature is enabled in the SYPCR
-               register.
+               support for the SoC. There must be support in the SoC
+               specific code for a watchdog. For the 8xx and 8260
+               CPUs, the SIU Watchdog feature is enabled in the SYPCR
+               register.  When supported for a specific SoC is
+               available, then no further board specific code should
+               be needed to use it.
+
+               CONFIG_HW_WATCHDOG
+               When using a watchdog circuitry external to the used
+               SoC, then define this variable and provide board
+               specific code for the "hw_watchdog_reset" function.
 
 - U-Boot Version:
                CONFIG_VERSION_VARIABLE
@@ -1322,7 +1345,6 @@ The following options need to be configured:
                driver in use must provide a function: mcast() to join/leave a
                multicast group.
 
-               CONFIG_BOOTP_RANDOM_DELAY
 - BOOTP Recovery Mode:
                CONFIG_BOOTP_RANDOM_DELAY
 
@@ -2218,7 +2240,7 @@ FIT uImage format:
 Modem Support:
 --------------
 
-[so far only for SMDK2400 and TRAB boards]
+[so far only for SMDK2400 boards]
 
 - Modem support enable:
                CONFIG_MODEM_SUPPORT
@@ -2906,6 +2928,14 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_SRIOn_MEM_SIZE:
                Size of SRIO port 'n' memory region
 
+- CONFIG_SYS_NDFC_16
+               Defined to tell the NDFC that the NAND chip is using a
+               16 bit bus.
+
+- CONFIG_SYS_NDFC_EBC0_CFG
+               Sets the EBC0_CFG register for the NDFC. If not defined
+               a default value will be used.
+
 - CONFIG_SPD_EEPROM
                Get DDR timing information from an I2C EEPROM. Common
                with pluggable memory modules such as SODIMMs
@@ -2918,6 +2948,12 @@ Low Level (hardware related) configuration options:
                one, specify here. Note that the value must resolve
                to something your driver can deal with.
 
+- CONFIG_SYS_DDR_RAW_TIMING
+               Get DDR timing information from other than SPD. Common with
+               soldered DDR chips onboard without SPD. DDR raw timing
+               parameters are extracted from datasheet and hard-coded into
+               header files or board specific files.
+
 - CONFIG_SYS_83XX_DDR_USES_CS0
                Only for 83xx systems. If specified, then DDR should
                be configured using CS0 and CS1 instead of CS2 and CS3.