mpc85xx/T1040QDS_D4: Add DDR4 support

[karo-tx-uboot.git] / README

diff --git a/README b/README
index 52a92e73b8e161126264aea58b4977119047c16d..bbd7399f53748d2b28ae5cc1e48ad6390a5a46bb 100644 (file)
--- a/README
+++ b/README
@@ -427,6 +427,10 @@ The following options need to be configured:
                In this mode, a single differential clock is used to supply
                clocks to the sysclock, ddrclock and usbclock.
 
+               CONFIG_SYS_CPC_REINIT_F
+               This CONFIG is defined when the CPC is configured as SRAM at the
+               time of U-boot entry and is required to be re-initialized.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -454,6 +458,9 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DDRC_GEN3
                Freescale DDR3 controller.
 
+               CONFIG_SYS_FSL_DDRC_GEN4
+               Freescale DDR4 controller.
+
                CONFIG_SYS_FSL_DDRC_ARM_GEN3
                Freescale DDR3 controller for ARM-based SoCs.
 
@@ -469,7 +476,15 @@ The following options need to be configured:
 
                CONFIG_SYS_FSL_DDR3
                Board config to use DDR3. It can be enabled for SoCs with
-               Freescale DDR3 controllers.
+               Freescale DDR3 or DDR3L controllers.
+
+               CONFIG_SYS_FSL_DDR3L
+               Board config to use DDR3L. It can be enabled for SoCs with
+               DDR3L controllers.
+
+               CONFIG_SYS_FSL_DDR4
+               Board config to use DDR4. It can be enabled for SoCs with
+               DDR4 controllers.
 
                CONFIG_SYS_FSL_IFC_BE
                Defines the IFC controller register space as Big Endian
@@ -4498,8 +4513,13 @@ This firmware often needs to be loaded during U-Boot booting, so macros
 are used to identify the storage device (NOR flash, SPI, etc) and the address
 within that device.
 
-- CONFIG_SYS_QE_FMAN_FW_ADDR
-       The address in the storage device where the firmware is located.  The
+- CONFIG_SYS_FMAN_FW_ADDR
+       The address in the storage device where the FMAN microcode is located.  The
+       meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+       is also specified.
+
+- CONFIG_SYS_QE_FW_ADDR
+       The address in the storage device where the QE microcode is located.  The
        meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
        is also specified.