]> git.kernelconcepts.de Git - karo-tx-linux.git/blobdiff - arch/arm/boot/dts/stih407-family.dtsi
Merge tag 'omap-for-v4.4/dt-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[karo-tx-linux.git] / arch / arm / boot / dts / stih407-family.dtsi
index eab3477e0a0e2f32f4f8c00303c3fd96230785dc..c944d3a5906d9eb0a3de96327766e3c2829ea9ec 100644 (file)
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       /* u-boot puts hpen in SBC dmem at 0xa4 offset */
+                       cpu-release-addr = <0x94100A4>;
                };
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       /* u-boot puts hpen in SBC dmem at 0xa4 offset */
+                       cpu-release-addr = <0x94100A4>;
                };
        };
 
                interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
        };
 
+       pwm_regulator: pwm-regulator {
+               compatible = "pwm-regulator";
+               pwms = <&pwm1 3 8448>;
+               regulator-name = "CPU_1V0_AVS";
+               regulator-min-microvolt = <784000>;
+               regulator-max-microvolt = <1299000>;
+               regulator-always-on;
+               max-duty-cycle = <255>;
+               status = "okay";
+       };
+
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
                                        <ST_IRQ_SYSCFG_DISABLED>;
                };
 
+               /* Display */
+               vtg_main: sti-vtg-main@8d02800 {
+                       compatible = "st,vtg";
+                       reg = <0x8d02800 0x200>;
+                       interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
+               };
+
+               vtg_aux: sti-vtg-aux@8d00200 {
+                       compatible = "st,vtg";
+                       reg = <0x8d00200 0x100>;
+                       interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
+               };
+
                serial@9830000 {
                        compatible = "st,asc";
                        reg = <0x9830000 0x2c>;
                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_spi1_default>;
 
                        status = "disabled";
                };
                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_spi2_default>;
 
                        status = "disabled";
                };
                        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_spi3_default>;
 
                        status = "disabled";
                };
                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_spi4_default>;
 
                        status = "disabled";
                };
                        interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk_sysin>;
                        clock-names = "ssc";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_spi10_default>;
 
                        status = "disabled";
                };
                        interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk_sysin>;
                        clock-names = "ssc";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_spi11_default>;
 
                        status = "disabled";
                };
                        interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk_sysin>;
                        clock-names = "ssc";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_spi12_default>;
 
                        status = "disabled";
                };
                        status = "disabled";
                };
 
+
                st_dwc3: dwc3@8f94000 {
                        compatible      = "st,stih407-dwc3";
                        reg             = <0x08f94000 0x1000>, <0x110 0x4>;
                                                  <&phy_port2 PHY_TYPE_USB3>;
                        };
                };
+
+               /* COMMS PWM Module */
+               pwm0: pwm@9810000 {
+                       compatible      = "st,sti-pwm";
+                       #pwm-cells      = <2>;
+                       reg             = <0x9810000 0x68>;
+                       pinctrl-names   = "default";
+                       pinctrl-0       = <&pinctrl_pwm0_chan0_default>;
+                       clock-names     = "pwm";
+                       clocks          = <&clk_sysin>;
+                       st,pwm-num-chan = <1>;
+
+                       status          = "disabled";
+               };
+
+               /* SBC PWM Module */
+               pwm1: pwm@9510000 {
+                       compatible      = "st,sti-pwm";
+                       #pwm-cells      = <2>;
+                       reg             = <0x9510000 0x68>;
+                       pinctrl-names   = "default";
+                       pinctrl-0       = <&pinctrl_pwm1_chan0_default
+                                       &pinctrl_pwm1_chan1_default
+                                       &pinctrl_pwm1_chan2_default
+                                       &pinctrl_pwm1_chan3_default>;
+                       clock-names     = "pwm";
+                       clocks          = <&clk_sysin>;
+                       st,pwm-num-chan = <4>;
+
+                       status          = "disabled";
+               };
+
+               rng10: rng@08a89000 {
+                       compatible      = "st,rng";
+                       reg             = <0x08a89000 0x1000>;
+                       clocks          = <&clk_sysin>;
+                       status          = "okay";
+               };
+
+               rng11: rng@08a8a000 {
+                       compatible      = "st,rng";
+                       reg             = <0x08a8a000 0x1000>;
+                       clocks          = <&clk_sysin>;
+                       status          = "okay";
+               };
+
+               ethernet0: dwmac@9630000 {
+                       device_type = "network";
+                       status = "disabled";
+                       compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+                       reg = <0x9630000 0x8000>, <0x80 0x4>;
+                       reg-names = "stmmaceth", "sti-ethconf";
+
+                       st,syscon = <&syscfg_sbc_reg 0x80>;
+                       st,gmac_en;
+                       resets = <&softreset STIH407_ETH1_SOFTRESET>;
+                       reset-names = "stmmaceth";
+
+                       interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
+                                    <GIC_SPI 99 IRQ_TYPE_NONE>;
+                       interrupt-names = "macirq", "eth_wake_irq";
+
+                       /* DMA Bus Mode */
+                       snps,pbl = <8>;
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_rgmii1>;
+
+                       clock-names = "stmmaceth", "sti-ethclk";
+                       clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
+                                <&clk_s_c0_flexgen CLK_ETH_PHY>;
+               };
        };
 };