#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/utils.h>
+#include <linux/compiler.h>
+
+static int emif1_enabled = -1, emif2_enabled = -1;
+
+void set_lpmode_selfrefresh(u32 base)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 reg;
+
+ reg = readl(&emif->emif_pwr_mgmt_ctrl);
+ reg &= ~EMIF_REG_LP_MODE_MASK;
+ reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
+ reg &= ~EMIF_REG_SR_TIM_MASK;
+ writel(reg, &emif->emif_pwr_mgmt_ctrl);
+
+ /* dummy read for the new SR_TIM to be loaded */
+ readl(&emif->emif_pwr_mgmt_ctrl);
+}
+
+void force_emif_self_refresh()
+{
+ set_lpmode_selfrefresh(EMIF1_BASE);
+ set_lpmode_selfrefresh(EMIF2_BASE);
+}
inline u32 emif_num(u32 base)
{
return 0;
}
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+u32 emif_sdram_type()
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+ return (readl(&emif->emif_sdram_config) &
+ EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+}
static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
{
mr = readl(&emif->emif_lpddr2_mode_reg_data);
debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
cs, mr_addr, mr);
- return mr;
+ if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
+ ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+ ((mr & 0xff000000) >> 24) == (mr & 0xff))
+ return mr & 0xff;
+ else
+ return mr;
}
static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
static void do_lpddr2_init(u32 base, u32 cs)
{
u32 mr_addr;
+ const struct lpddr2_mr_regs *mr_regs;
+ get_lpddr2_mr_regs(&mr_regs);
/* Wait till device auto initialization is complete */
while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
;
- set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+ set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
/*
* tZQINIT = 1 us
* Enough loops assuming a maximum of 2GHz
sdelay(2000);
- if (omap_revision() >= OMAP5430_ES1_0)
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
- else
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
-
- set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+ set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
+ set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
/*
* Enable refresh along with writing MR2
* Encoding of RL in MR2 is (RL - 2)
*/
mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
- set_mr(base, cs, mr_addr, RL_FINAL - 2);
+ set_mr(base, cs, mr_addr, mr_regs->mr2);
- if (omap_revision() >= OMAP5430_ES1_0)
- set_mr(base, cs, LPDDR2_MR3, 0x1);
+ if (mr_regs->mr3 > 0)
+ set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
}
static void lpddr2_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- u32 i = 0;
/* Not NVM */
clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
- ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
- if (omap_revision() >= OMAP5430_ES1_0) {
- /* Configure external phy control timing registers */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
-
- /*
- * external phy 6-24 registers do not change with
- * ddr frequency
- */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
- writel(ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- }
- }
+ do_ext_phy_settings(base, regs);
do_lpddr2_init(base, CS0);
if (regs->sdram_config & EMIF_REG_EBANK_MASK)
/* Enable refresh now */
clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
+ }
+
+__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
}
void emif_update_timings(u32 base, const struct emif_regs *regs)
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- u32 i = 0;
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
- ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
- /* Configure external phy control timing registers */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
-
- /*
- * external phy 6-24 registers do not change with
- * ddr frequency
- */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
- writel(ddr3_ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ddr3_ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- }
+ do_ext_phy_settings(base, regs);
/* enable leveling */
writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
}
mr = get_mr(base, cs, LPDDR2_MR5);
- if (mr >= 0xFF) {
+ if (mr > 0xFF) {
/* Mode register value bigger than 8 bit */
return 0;
}
* OPP to another)
*/
if (!(in_sdram || warm_reset())) {
- if (omap_revision() != OMAP5432_ES1_0)
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
lpddr2_init(base, regs);
else
ddr3_init(base, regs);
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 omap_rev = omap_revision();
- if (omap_rev == OMAP5430_ES1_0)
- return;
-
/* reset phy on ES2.0 */
if (omap_rev == OMAP4430_ES2_0)
emif_reset_phy(base);
void dmm_init(u32 base)
{
const struct dmm_lisa_map_regs *lisa_map_regs;
+ u32 i, section, valid;
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
emif_get_dmm_regs(&lisa_map_regs);
writel(lisa_map_regs->dmm_lisa_map_0,
&hw_lisa_map_regs->dmm_lisa_map_0);
- if (omap_revision() >= OMAP4460_ES1_0) {
+ if (lisa_map_regs->is_ma_present) {
hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)MA_BASE;
writel(lisa_map_regs->dmm_lisa_map_0,
&hw_lisa_map_regs->dmm_lisa_map_0);
}
+
+ /*
+ * EMIF should be configured only when
+ * memory is mapped on it. Using emif1_enabled
+ * and emif2_enabled variables for this.
+ */
+ emif1_enabled = 0;
+ emif2_enabled = 0;
+ for (i = 0; i < 4; i++) {
+ section = __raw_readl(DMM_BASE + i*4);
+ valid = (section & EMIF_SDRC_MAP_MASK) >>
+ (EMIF_SDRC_MAP_SHIFT);
+ if (valid == 3) {
+ emif1_enabled = 1;
+ emif2_enabled = 1;
+ break;
+ } else if (valid == 1) {
+ emif1_enabled = 1;
+ } else if (valid == 2) {
+ emif2_enabled = 1;
+ }
+ }
+
}
/*
void sdram_init(void)
{
u32 in_sdram, size_prog, size_detect;
- u32 omap_rev = omap_revision();
+ u32 sdram_type = emif_sdram_type();
debug(">>sdram_init()\n");
debug("in_sdram = %d\n", in_sdram);
if (!(in_sdram || warm_reset())) {
- if (omap_rev != OMAP5432_ES1_0)
- bypass_dpll(&prcm->cm_clkmode_dpll_core);
+ if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
+ bypass_dpll((*prcm)->cm_clkmode_dpll_core);
else
- writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
+ writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
}
- do_sdram_init(EMIF1_BASE);
- do_sdram_init(EMIF2_BASE);
-
if (!in_sdram)
dmm_init(DMM_BASE);
+ if (emif1_enabled)
+ do_sdram_init(EMIF1_BASE);
+
+ if (emif2_enabled)
+ do_sdram_init(EMIF2_BASE);
+
if (!(in_sdram || warm_reset())) {
- emif_post_init_config(EMIF1_BASE);
- emif_post_init_config(EMIF2_BASE);
+ if (emif1_enabled)
+ emif_post_init_config(EMIF1_BASE);
+ if (emif2_enabled)
+ emif_post_init_config(EMIF2_BASE);
}
/* for the shadow registers to take effect */
- if (omap_rev != OMAP5432_ES1_0)
+ if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
freq_update_core();
/* Do some testing after the init */