ARM: OMAP5: DRA7xx: Add support for power rail grouping

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap5 / hw_data.c

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 95f16866e6cbd9e043dcdf969a937e648bbd13a8..b9734fea8febaea9cf3cd805c4090a038d5337e0 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -320,6 +320,7 @@ struct pmic_data palmas = {
        .pmic_write     = omap_vc_bypass_send_value,
 };
 
+/* The TPS659038 and TPS65917 are software-compatible, use common struct */
 struct pmic_data tps659038 = {
        .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
        .step = 10000, /* 10 mV represented in uV */
@@ -394,34 +395,38 @@ struct vcores_data dra752_volts = {
 };
 
 struct vcores_data dra722_volts = {
-       .mpu.value      = 1000,
+       .mpu.value      = VDD_MPU_DRA72x,
        .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
-       .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .mpu.addr       = 0x23,
+       .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .mpu.addr       = TPS65917_REG_ADDR_SMPS1,
        .mpu.pmic       = &tps659038,
 
-       .eve.value      = 1000,
-       .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
-       .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .eve.addr       = 0x2f,
-       .eve.pmic       = &tps659038,
+       .core.value     = VDD_CORE_DRA72x,
+       .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+       .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .core.addr      = TPS65917_REG_ADDR_SMPS2,
+       .core.pmic      = &tps659038,
 
-       .gpu.value      = 1000,
+       /*
+        * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
+        * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
+        */
+       .gpu.value      = VDD_GPU_DRA72x,
        .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
-       .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .gpu.addr       = 0x2f,
+       .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .gpu.addr       = TPS65917_REG_ADDR_SMPS3,
        .gpu.pmic       = &tps659038,
 
-       .core.value     = 1000,
-       .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
-       .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-       .core.addr      = 0x27,
-       .core.pmic      = &tps659038,
+       .eve.value      = VDD_EVE_DRA72x,
+       .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+       .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .eve.addr       = TPS65917_REG_ADDR_SMPS3,
+       .eve.pmic       = &tps659038,
 
-       .iva.value      = 1000,
+       .iva.value      = VDD_IVA_DRA72x,
        .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
-       .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .iva.addr       = 0x2f,
+       .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .iva.addr       = TPS65917_REG_ADDR_SMPS3,
        .iva.pmic       = &tps659038,
 };