ARM: OMAP4+: Make control module register structure generic

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap5 / prcm-regs.c

diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index cdc4864919fdea367b1b187aef48b8a89ce437d6..0f58b2f1a7ccc269c2aacdd94350637415f363f3 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -304,3 +304,77 @@ struct prcm_regs const omap5_es1_prcm = {
        .prm_sldo_mm_setup = 0x4ae07bd4,
        .prm_sldo_mm_ctrl = 0x4ae07bd8,
 };
+
+struct omap_sys_ctrl_regs const omap5_ctrl = {
+       .control_status                         = 0x4A002134,
+       .control_paconf_global                  = 0x4A002DA0,
+       .control_paconf_mode                    = 0x4A002DA4,
+       .control_smart1io_padconf_0             = 0x4A002DA8,
+       .control_smart1io_padconf_1             = 0x4A002DAC,
+       .control_smart1io_padconf_2             = 0x4A002DB0,
+       .control_smart2io_padconf_0             = 0x4A002DB4,
+       .control_smart2io_padconf_1             = 0x4A002DB8,
+       .control_smart2io_padconf_2             = 0x4A002DBC,
+       .control_smart3io_padconf_0             = 0x4A002DC0,
+       .control_smart3io_padconf_1             = 0x4A002DC4,
+       .control_pbias                          = 0x4A002E00,
+       .control_i2c_0                          = 0x4A002E04,
+       .control_camera_rx                      = 0x4A002E08,
+       .control_hdmi_tx_phy                    = 0x4A002E0C,
+       .control_uniportm                       = 0x4A002E10,
+       .control_dsiphy                         = 0x4A002E14,
+       .control_mcbsplp                        = 0x4A002E18,
+       .control_usb2phycore                    = 0x4A002E1C,
+       .control_hdmi_1                         = 0x4A002E20,
+       .control_hsi                            = 0x4A002E24,
+       .control_ddr3ch1_0                      = 0x4A002E30,
+       .control_ddr3ch2_0                      = 0x4A002E34,
+       .control_ddrch1_0                       = 0x4A002E38,
+       .control_ddrch1_1                       = 0x4A002E3C,
+       .control_ddrch2_0                       = 0x4A002E40,
+       .control_ddrch2_1                       = 0x4A002E44,
+       .control_lpddr2ch1_0                    = 0x4A002E48,
+       .control_lpddr2ch1_1                    = 0x4A002E4C,
+       .control_ddrio_0                        = 0x4A002E50,
+       .control_ddrio_1                        = 0x4A002E54,
+       .control_ddrio_2                        = 0x4A002E58,
+       .control_hyst_1                         = 0x4A002E5C,
+       .control_usbb_hsic_control              = 0x4A002E60,
+       .control_c2c                            = 0x4A002E64,
+       .control_core_control_spare_rw          = 0x4A002E68,
+       .control_core_control_spare_r           = 0x4A002E6C,
+       .control_core_control_spare_r_c0        = 0x4A002E70,
+       .control_srcomp_north_side              = 0x4A002E74,
+       .control_srcomp_south_side              = 0x4A002E78,
+       .control_srcomp_east_side               = 0x4A002E7C,
+       .control_srcomp_west_side               = 0x4A002E80,
+       .control_srcomp_code_latch              = 0x4A002E84,
+       .control_port_emif1_sdram_config        = 0x4AE0C110,
+       .control_port_emif1_lpddr2_nvm_config   = 0x4AE0C114,
+       .control_port_emif2_sdram_config        = 0x4AE0C118,
+       .control_emif1_sdram_config_ext         = 0x4AE0C144,
+       .control_emif2_sdram_config_ext         = 0x4AE0C148,
+       .control_smart1nopmio_padconf_0         = 0x4AE0CDA0,
+       .control_smart1nopmio_padconf_1         = 0x4AE0CDA4,
+       .control_padconf_mode                   = 0x4AE0CDA8,
+       .control_xtal_oscillator                = 0x4AE0CDAC,
+       .control_i2c_2                          = 0x4AE0CDB0,
+       .control_ckobuffer                      = 0x4AE0CDB4,
+       .control_wkup_control_spare_rw          = 0x4AE0CDB8,
+       .control_wkup_control_spare_r           = 0x4AE0CDBC,
+       .control_wkup_control_spare_r_c0        = 0x4AE0CDC0,
+       .control_srcomp_east_side_wkup          = 0x4AE0CDC4,
+       .control_efuse_1                        = 0x4AE0CDC8,
+       .control_efuse_2                        = 0x4AE0CDCC,
+       .control_efuse_3                        = 0x4AE0CDD0,
+       .control_efuse_4                        = 0x4AE0CDD4,
+       .control_efuse_5                        = 0x4AE0CDD8,
+       .control_efuse_6                        = 0x4AE0CDDC,
+       .control_efuse_7                        = 0x4AE0CDE0,
+       .control_efuse_8                        = 0x4AE0CDE4,
+       .control_efuse_9                        = 0x4AE0CDE8,
+       .control_efuse_10                       = 0x4AE0CDEC,
+       .control_efuse_11                       = 0x4AE0CDF0,
+       .control_efuse_12                       = 0x4AE0CDF4,
+       .control_efuse_13                       = 0x4AE0CDF8,
+};