/* UARTs which we can enable */
UARTA = 1 << 0,
UARTB = 1 << 1,
+ UARTC = 1 << 2,
UARTD = 1 << 3,
- UART_COUNT = 4,
+ UARTE = 1 << 4,
+ UART_COUNT = 5,
};
/*
case 3:
return 0x40000000; /* 1GB */
}
-#else /* Tegra30 */
+#else /* Tegra30/Tegra114 */
/* bits 31:28 in OdmData are used for RAM size on T30 */
switch ((reg) >> 28) {
case 0:
FUNCMUX_UART1_SDIO1,
#else
FUNCMUX_UART1_IRRX_IRTX,
- #endif
- FUNCMUX_UART2_IRDA,
+#endif
+ FUNCMUX_UART2_UAD,
-1,
FUNCMUX_UART4_GMC,
-1,
-#else /* Tegra30 */
+#elif defined(CONFIG_TEGRA30)
FUNCMUX_UART1_ULPI, /* UARTA */
-1,
-1,
-1,
-1,
+#else /* Tegra114 */
+ -1,
+ -1,
+ -1,
+ FUNCMUX_UART4_GMI, /* UARTD */
+ -1,
#endif
};
PERIPH_ID_UART2,
PERIPH_ID_UART3,
PERIPH_ID_UART4,
+ PERIPH_ID_UART5,
};
size_t i;
#ifdef CONFIG_TEGRA_ENABLE_UARTB
uart_ids |= UARTB;
#endif
+#ifdef CONFIG_TEGRA_ENABLE_UARTC
+ uart_ids |= UARTC;
+#endif
#ifdef CONFIG_TEGRA_ENABLE_UARTD
uart_ids |= UARTD;
+#endif
+#ifdef CONFIG_TEGRA_ENABLE_UARTE
+ uart_ids |= UARTE;
#endif
setup_uarts(uart_ids);
}