#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
+/* Micron MT41K256M16HA-125E */
+#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100006
+#define MT41K256M16HA125E_EMIF_TIM1 0x0888A39B
+#define MT41K256M16HA125E_EMIF_TIM2 0x26517FDA
+#define MT41K256M16HA125E_EMIF_TIM3 0x501F84EF
+#define MT41K256M16HA125E_EMIF_SDCFG 0x61C04BB2
+#define MT41K256M16HA125E_EMIF_SDREF 0x0000093B
+#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
+#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
+#define MT41K256M16HA125E_RATIO 0x40
+#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
+#define MT41K256M16HA125E_RD_DQS 0x3C
+#define MT41K256M16HA125E_WR_DQS 0x45
+#define MT41K256M16HA125E_PHY_WR_DATA 0x7F
+#define MT41K256M16HA125E_PHY_FIFO_WE 0x9B
+#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
+
/* Micron MT41J512M8RH-125 on EVM v1.5 */
#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B