sun6i: Add a sigma_delta_enable paramter to clock_set_pll5()

[karo-tx-uboot.git] / arch / arm / include / asm / arch-ep93xx / ep93xx.h

diff --git a/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/arch/arm/include/asm/arch-ep93xx/ep93xx.h
index 806557a50ea27190890ed7a455453c741bb18fb4..330493b6065e5d7996a2411021304cb55cdbdcc6 100644 (file)
--- a/arch/arm/include/asm/arch-ep93xx/ep93xx.h
+++ b/arch/arm/include/asm/arch-ep93xx/ep93xx.h
@@ -1,6 +1,9 @@
 /*
  * Cirrus Logic EP93xx register definitions.
  *
+ * Copyright (C) 2013
+ * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+ *
  * Copyright (C) 2009
  * Matthias Kaehlcke <matthias@kaehlcke.net>
  *
@@ -16,21 +19,7 @@
  * Copyright (C) 2003 Cirrus Logic, Inc
  * Copyright (C) 1999 ARM Limited.
  *
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #define EP93XX_AHB_BASE                        0x80000000
@@ -301,6 +290,20 @@ struct sdram_regs {
 #define SDRAM_DEVCFG_CASLAT_2          0x00010000
 #define SDRAM_DEVCFG_RASTOCAS_2                0x00200000
 
+#define SDRAM_OFF_GLCONFIG             0x0004
+#define SDRAM_OFF_REFRSHTIMR           0x0008
+
+#define SDRAM_OFF_DEVCFG0              0x0010
+#define SDRAM_OFF_DEVCFG1              0x0014
+#define SDRAM_OFF_DEVCFG2              0x0018
+#define SDRAM_OFF_DEVCFG3              0x001C
+
+#define SDRAM_DEVCFG0_BASE             0xC0000000
+#define SDRAM_DEVCFG1_BASE             0xD0000000
+#define SDRAM_DEVCFG2_BASE             0xE0000000
+#define SDRAM_DEVCFG3_ASD0_BASE                0xF0000000
+#define SDRAM_DEVCFG3_ASD1_BASE                0x00000000
+
 #define GLCONFIG_INIT                  (1 << 0)
 #define GLCONFIG_MRS                   (1 << 1)
 #define GLCONFIG_SMEMBUSY              (1 << 5)
@@ -309,6 +312,43 @@ struct sdram_regs {
 #define GLCONFIG_CLKSHUTDOWN           (1 << 30)
 #define GLCONFIG_CKE                   (1 << 31)
 
+#define EP93XX_SDRAMCTRL                       0x80060000
+#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT                0x00000001
+#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS         0x00000002
+#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY    0x00000020
+#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR         0x00000040
+#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN     0x00000080
+#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000
+#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE         0x80000000
+
+#define EP93XX_SDRAMCTRL_REFRESH_MASK          0x0000FFFF
+
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32   0x00000002
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16   0x00000001
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8    0x00000000
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA      0x00000004
+
+#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH    0x00000004
+#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT      0x00000008
+#define EP93XX_SDRAMCTRL_DEVCFG_SROM512                0x00000010
+#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL         0x00000020
+#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE         0x00000040
+#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR   0x00000080
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK    0x00070000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2       0x00010000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3       0x00020000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4       0x00030000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5       0x00040000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6       0x00050000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7       0x00060000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8       0x00070000
+#define EP93XX_SDRAMCTRL_DEVCFG_WBL            0x00080000
+#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK  0x00300000
+#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2     0x00200000
+#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3     0x00300000
+#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE  0x01000000
+
 /*
  * 0x80070000 - 0x8007FFFF: Reserved
  */
@@ -338,6 +378,13 @@ struct smc_regs {
 };
 #endif
 
+#define EP93XX_OFF_SMCBCR0             0x00
+#define EP93XX_OFF_SMCBCR1             0x04
+#define EP93XX_OFF_SMCBCR2             0x08
+#define EP93XX_OFF_SMCBCR3             0x0C
+#define EP93XX_OFF_SMCBCR6             0x18
+#define EP93XX_OFF_SMCBCR7             0x1C
+
 #define SMC_BCR_IDCY_SHIFT     0
 #define SMC_BCR_WST1_SHIFT     5
 #define SMC_BCR_BLE            (1 << 10)
@@ -459,6 +506,14 @@ struct gpio_regs {
 };
 #endif
 
+#define EP93XX_LED_DATA                0x80840020
+#define EP93XX_LED_GREEN_ON    0x0001
+#define EP93XX_LED_RED_ON      0x0002
+
+#define EP93XX_LED_DDR         0x80840024
+#define EP93XX_LED_GREEN_ENABLE        0x0001
+#define EP93XX_LED_RED_ENABLE  0x00020000
+
 /*
  * 0x80850000 - 0x8087FFFF: Reserved
  */
@@ -533,6 +588,9 @@ struct gpio_regs {
 #define SYSCON_OFFSET          0x930000
 #define SYSCON_BASE            (EP93XX_APB_BASE | SYSCON_OFFSET)
 
+/* Security */
+#define SECURITY_EXTENSIONID   0x80832714
+
 #ifndef __ASSEMBLY__
 struct syscon_regs {
        uint32_t pwrsts;
@@ -567,7 +625,11 @@ struct syscon_regs {
 #define SYSCON_SCRATCH0                (SYSCON_BASE + 0x0040)
 #endif
 
+#define SYSCON_OFF_CLKSET1                     0x0020
+#define SYSCON_OFF_SYSCFG                      0x009c
+
 #define SYSCON_PWRCNT_UART_BAUD                        (1 << 29)
+#define SYSCON_PWRCNT_USH_EN                   (1 << 28)
 
 #define SYSCON_CLKSET_PLL_X2IPD_SHIFT          0
 #define SYSCON_CLKSET_PLL_X2FBD2_SHIFT         5
@@ -585,6 +647,8 @@ struct syscon_regs {
 #define SYSCON_CHIPID_REV_MASK                 0xF0000000
 #define SYSCON_DEVICECFG_SWRST                 (1 << 31)
 
+#define SYSCON_SYSCFG_LASDO                    0x00000020
+
 /*
  * 0x80930000 - 0x8093FFFF: Watchdog Timer
  */
@@ -594,3 +658,10 @@ struct syscon_regs {
 /*
  * 0x80950000 - 0x9000FFFF: Reserved
  */
+
+/*
+ * During low_level init we store memory layout in memory at specific location
+ */
+#define UBOOT_MEMORYCNF_BANK_SIZE              0x2000
+#define UBOOT_MEMORYCNF_BANK_MASK              0x2004
+#define UBOOT_MEMORYCNF_BANK_COUNT             0x2008