Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

[karo-tx-uboot.git] / arch / arm / include / asm / arch-exynos / cpu.h

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 573f75553ba312f5a68ab0d524ec0ec5998fc286..29674ad4dadda7942531df19b2495b535b8ec37d 100644 (file)
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -25,9 +25,12 @@
 #define EXYNOS4_SYSTIMER_BASE          0x10050000
 #define EXYNOS4_WATCHDOG_BASE          0x10060000
 #define EXYNOS4_TZPC_BASE              0x10110000
-#define EXYNOS4_MIU_BASE               0x10600000
 #define EXYNOS4_DMC_CTRL_BASE          0x10400000
+#define EXYNOS4_MIU_BASE               0x10600000
+#define EXYNOS4_ACE_SFR_BASE           0x10830000
 #define EXYNOS4_GPIO_PART2_BASE                0x11000000
+#define EXYNOS4_GPIO_PART2_0           0x11000000 /* GPJ0 */
+#define EXYNOS4_GPIO_PART2_1           0x11000c00 /* GPX0 */
 #define EXYNOS4_GPIO_PART1_BASE                0x11400000
 #define EXYNOS4_FIMD_BASE              0x11C00000
 #define EXYNOS4_MIPI_DSIM_BASE         0x11C80000
@@ -48,7 +51,6 @@
 #define EXYNOS4_GPIO_PART4_BASE                DEVICE_NOT_AVAILABLE
 #define EXYNOS4_DP_BASE                        DEVICE_NOT_AVAILABLE
 #define EXYNOS4_SPI_ISP_BASE           DEVICE_NOT_AVAILABLE
-#define EXYNOS4_ACE_SFR_BASE           DEVICE_NOT_AVAILABLE
 #define EXYNOS4_DMC_PHY_BASE           DEVICE_NOT_AVAILABLE
 #define EXYNOS4_AUDIOSS_BASE           DEVICE_NOT_AVAILABLE
 #define EXYNOS4_USB_HOST_XHCI_BASE     DEVICE_NOT_AVAILABLE
@@ -68,8 +70,16 @@
 #define EXYNOS4X12_TZPC_BASE           0x10110000
 #define EXYNOS4X12_DMC_CTRL_BASE       0x10600000
 #define EXYNOS4X12_GPIO_PART4_BASE     0x106E0000
+#define EXYNOS4X12_ACE_SFR_BASE                0x10830000
 #define EXYNOS4X12_GPIO_PART2_BASE     0x11000000
+#define EXYNOS4X12_GPIO_PART2_0                0x11000000
+#define EXYNOS4X12_GPIO_PART2_1                0x11000040 /* GPK0 */
+#define EXYNOS4X12_GPIO_PART2_2                0x11000260 /* GPM0 */
+#define EXYNOS4X12_GPIO_PART2_3                0x11000c00 /* GPX0 */
 #define EXYNOS4X12_GPIO_PART1_BASE     0x11400000
+#define EXYNOS4X12_GPIO_PART1_0                0x11400000 /* GPA0 */
+#define EXYNOS4X12_GPIO_PART1_1                0x11400180 /* GPF0 */
+#define EXYNOS4X12_GPIO_PART1_2                0x11400240 /* GPJ0 */
 #define EXYNOS4X12_FIMD_BASE           0x11C00000
 #define EXYNOS4X12_MIPI_DSIM_BASE      0x11C80000
 #define EXYNOS4X12_USBOTG_BASE         0x12480000
@@ -87,7 +97,6 @@
 #define EXYNOS4X12_I2S_BASE            DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_BASE            DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_ISP_BASE                DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_ACE_SFR_BASE                DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_DMC_PHY_BASE                DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_AUDIOSS_BASE                DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_USB_HOST_XHCI_BASE  DEVICE_NOT_AVAILABLE
@@ -98,7 +107,7 @@
 #define EXYNOS5_I2C_SPACING            0x10000
 
 #define EXYNOS5_AUDIOSS_BASE           0x03810000
-#define EXYNOS5_GPIO_PART4_BASE                0x03860000
+#define EXYNOS5_GPIO_PART8_BASE                0x03860000
 #define EXYNOS5_PRO_ID                 0x10000000
 #define EXYNOS5_CLOCK_BASE             0x10010000
 #define EXYNOS5_POWER_BASE             0x10040000
@@ -106,11 +115,15 @@
 #define EXYNOS5_SYSREG_BASE            0x10050000
 #define EXYNOS5_TZPC_BASE              0x10100000
 #define EXYNOS5_WATCHDOG_BASE          0x101D0000
-#define EXYNOS5_ACE_SFR_BASE            0x10830000
+#define EXYNOS5_ACE_SFR_BASE           0x10830000
 #define EXYNOS5_DMC_PHY_BASE           0x10C00000
-#define EXYNOS5_GPIO_PART3_BASE                0x10D10000
+#define EXYNOS5_GPIO_PART5_BASE                0x10D10000
+#define EXYNOS5_GPIO_PART6_BASE                0x10D10060
+#define EXYNOS5_GPIO_PART7_BASE                0x10D100C0
 #define EXYNOS5_DMC_CTRL_BASE          0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE                0x11400000
+#define EXYNOS5_GPIO_PART2_BASE                0x114002E0
+#define EXYNOS5_GPIO_PART3_BASE                0x11400C00
 #define EXYNOS5_MIPI_DSIM_BASE         0x11D00000
 #define EXYNOS5_USB_HOST_XHCI_BASE     0x12000000
 #define EXYNOS5_USB3PHY_BASE           0x12100000
@@ -125,7 +138,7 @@
 #define EXYNOS5_I2S_BASE               0x12D60000
 #define EXYNOS5_PWMTIMER_BASE          0x12DD0000
 #define EXYNOS5_SPI_ISP_BASE           0x131A0000
-#define EXYNOS5_GPIO_PART2_BASE                0x13400000
+#define EXYNOS5_GPIO_PART4_BASE                0x13400000
 #define EXYNOS5_FIMD_BASE              0x14400000
 #define EXYNOS5_DP_BASE                        0x145B0000
 
@@ -135,7 +148,7 @@
 
 /* EXYNOS5420 */
 #define EXYNOS5420_AUDIOSS_BASE                0x03810000
-#define EXYNOS5420_GPIO_PART5_BASE     0x03860000
+#define EXYNOS5420_GPIO_PART6_BASE     0x03860000
 #define EXYNOS5420_PRO_ID              0x10000000
 #define EXYNOS5420_CLOCK_BASE          0x10010000
 #define EXYNOS5420_POWER_BASE          0x10040000
@@ -158,8 +171,9 @@
 #define EXYNOS5420_PWMTIMER_BASE       0x12DD0000
 #define EXYNOS5420_SPI_ISP_BASE                0x131A0000
 #define EXYNOS5420_GPIO_PART2_BASE     0x13400000
-#define EXYNOS5420_GPIO_PART3_BASE     0x13410000
-#define EXYNOS5420_GPIO_PART4_BASE     0x14000000
+#define EXYNOS5420_GPIO_PART3_BASE     0x13400C00
+#define EXYNOS5420_GPIO_PART4_BASE     0x13410000
+#define EXYNOS5420_GPIO_PART5_BASE     0x14000000
 #define EXYNOS5420_GPIO_PART1_BASE     0x14010000
 #define EXYNOS5420_MIPI_DSIM_BASE      0x14500000
 #define EXYNOS5420_DP_BASE             0x145B0000
@@ -185,9 +199,11 @@ static inline int s5p_get_cpu_rev(void)
 
 static inline void s5p_set_cpu_id(void)
 {
-       unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
+       unsigned int pro_id = readl(EXYNOS4_PRO_ID);
+       unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12;
+       unsigned int cpu_rev = pro_id & 0x000000FF;
 
-       switch (pro_id) {
+       switch (cpu_id) {
        case 0x200:
                /* Exynos4210 EVT0 */
                s5p_cpu_id = 0x4210;
@@ -196,10 +212,12 @@ static inline void s5p_set_cpu_id(void)
        case 0x210:
                /* Exynos4210 EVT1 */
                s5p_cpu_id = 0x4210;
+               s5p_cpu_rev = cpu_rev;
                break;
        case 0x412:
                /* Exynos4412 */
                s5p_cpu_id = 0x4412;
+               s5p_cpu_rev = cpu_rev;
                break;
        case 0x520:
                /* Exynos5250 */
@@ -209,6 +227,13 @@ static inline void s5p_set_cpu_id(void)
                /* Exynos5420 */
                s5p_cpu_id = 0x5420;
                break;
+       case 0x422:
+               /*
+                * Exynos5800 is a variant of Exynos5420
+                * and has product id 0x5422
+                */
+               s5p_cpu_id = 0x5800;
+               break;
        }
 }
 
@@ -237,6 +262,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210)
 IS_EXYNOS_TYPE(exynos4412, 0x4412)
 IS_EXYNOS_TYPE(exynos5250, 0x5250)
 IS_EXYNOS_TYPE(exynos5420, 0x5420)
+IS_EXYNOS_TYPE(exynos5800, 0x5800)
 
 #define SAMSUNG_BASE(device, base)                             \
 static inline unsigned int __attribute__((no_instrument_function)) \
@@ -247,7 +273,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \
                        return EXYNOS4X12_##base;               \
                return EXYNOS4_##base;                          \
        } else if (cpu_is_exynos5()) {                          \
-               if (proid_is_exynos5420())                      \
+               if (proid_is_exynos5420() || proid_is_exynos5800())     \
                        return EXYNOS5420_##base;               \
                return EXYNOS5_##base;                          \
        }                                                       \