Merge branch 'master' of git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / arch / arm / include / asm / arch-exynos / dmc.h

diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h
index bd52d16c9d40c748e545b6ebf6374c5fa0ae9b77..f65c676cc590d301ed144266a206b77bb6ef8214 100644 (file)
--- a/arch/arm/include/asm/arch-exynos/dmc.h
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -251,5 +251,70 @@ struct exynos5_phy_control {
        unsigned int phy_con41;
        unsigned int phy_con42;
 };
+
+enum ddr_mode {
+       DDR_MODE_DDR2,
+       DDR_MODE_DDR3,
+       DDR_MODE_LPDDR2,
+       DDR_MODE_LPDDR3,
+
+       DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+       MEM_MANUF_AUTODETECT,
+       MEM_MANUF_ELPIDA,
+       MEM_MANUF_SAMSUNG,
+
+       MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT        28
+#define CONCONTROL_RD_FETCH_SHIFT      12
+#define CONCONTROL_RD_FETCH_MASK       (0x7 << CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT       5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT       24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT   0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT    16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT       17
+#define PHY_CON0_T_WRRDCMD_MASK                (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT   11
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT        0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT       24
+#define PHY_CON12_CTRL_INC_SHIFT       16
+#define PHY_CON12_CTRL_FORCE_SHIFT     8
+#define PHY_CON12_CTRL_START_SHIFT     6
+#define PHY_CON12_CTRL_START_MASK      (1 << PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT    5
+#define PHY_CON12_CTRL_DLL_ON_MASK     (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT       1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT    24
+#define PHY_CON16_ZQ_MODE_DDS_MASK     (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK    (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK  (1 << 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT    8
+#define PHY_CON42_CTRL_BSTLEN_MASK     (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT     0
+#define PHY_CON42_CTRL_RDLAT_MASK      (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
+
 #endif
 #endif