Merge branch 'master' of git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / arch / arm / include / asm / arch-exynos / dmc.h

diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h
index debbe503107d161dc280128fe23c0b2961f29d02..f65c676cc590d301ed144266a206b77bb6ef8214 100644 (file)
--- a/arch/arm/include/asm/arch-exynos/dmc.h
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -2,6 +2,115 @@
 #define __DMC_H__
 
 #ifndef __ASSEMBLY__
+struct exynos4_dmc {
+       unsigned int concontrol;
+       unsigned int memcontrol;
+       unsigned int memconfig0;
+       unsigned int memconfig1;
+       unsigned int directcmd;
+       unsigned int prechconfig;
+       unsigned int phycontrol0;
+       unsigned int phycontrol1;
+       unsigned int phycontrol2;
+       unsigned int phycontrol3;
+       unsigned int pwrdnconfig;
+       unsigned char res1[0x4];
+       unsigned int timingref;
+       unsigned int timingrow;
+       unsigned int timingdata;
+       unsigned int timingpower;
+       unsigned int phystatus;
+       unsigned int phyzqcontrol;
+       unsigned int chip0status;
+       unsigned int chip1status;
+       unsigned int arefstatus;
+       unsigned int mrstatus;
+       unsigned int phytest0;
+       unsigned int phytest1;
+       unsigned int qoscontrol0;
+       unsigned int qosconfig0;
+       unsigned int qoscontrol1;
+       unsigned int qosconfig1;
+       unsigned int qoscontrol2;
+       unsigned int qosconfig2;
+       unsigned int qoscontrol3;
+       unsigned int qosconfig3;
+       unsigned int qoscontrol4;
+       unsigned int qosconfig4;
+       unsigned int qoscontrol5;
+       unsigned int qosconfig5;
+       unsigned int qoscontrol6;
+       unsigned int qosconfig6;
+       unsigned int qoscontrol7;
+       unsigned int qosconfig7;
+       unsigned int qoscontrol8;
+       unsigned int qosconfig8;
+       unsigned int qoscontrol9;
+       unsigned int qosconfig9;
+       unsigned int qoscontrol10;
+       unsigned int qosconfig10;
+       unsigned int qoscontrol11;
+       unsigned int qosconfig11;
+       unsigned int qoscontrol12;
+       unsigned int qosconfig12;
+       unsigned int qoscontrol13;
+       unsigned int qosconfig13;
+       unsigned int qoscontrol14;
+       unsigned int qosconfig14;
+       unsigned int qoscontrol15;
+       unsigned int qosconfig15;
+       unsigned int qostimeout0;
+       unsigned int qostimeout1;
+       unsigned char res2[0x8];
+       unsigned int ivcontrol;
+       unsigned char res3[0x8];
+       unsigned int perevconfig;
+       unsigned char res4[0xDF00];
+       unsigned int pmnc_ppc_a;
+       unsigned char res5[0xC];
+       unsigned int cntens_ppc_a;
+       unsigned char res6[0xC];
+       unsigned int cntenc_ppc_a;
+       unsigned char res7[0xC];
+       unsigned int intens_ppc_a;
+       unsigned char res8[0xC];
+       unsigned int intenc_ppc_a;
+       unsigned char res9[0xC];
+       unsigned int flag_ppc_a;
+       unsigned char res10[0xAC];
+       unsigned int ccnt_ppc_a;
+       unsigned char res11[0xC];
+       unsigned int pmcnt0_ppc_a;
+       unsigned char res12[0xC];
+       unsigned int pmcnt1_ppc_a;
+       unsigned char res13[0xC];
+       unsigned int pmcnt2_ppc_a;
+       unsigned char res14[0xC];
+       unsigned int pmcnt3_ppc_a;
+       unsigned char res15[0xEBC];
+       unsigned int pmnc_ppc_m;
+       unsigned char res16[0xC];
+       unsigned int cntens_ppc_m;
+       unsigned char res17[0xC];
+       unsigned int cntenc_ppc_m;
+       unsigned char res18[0xC];
+       unsigned int intens_ppc_m;
+       unsigned char res19[0xC];
+       unsigned int intenc_ppc_m;
+       unsigned char res20[0xC];
+       unsigned int flag_ppc_m;
+       unsigned char res21[0xAC];
+       unsigned int ccnt_ppc_m;
+       unsigned char res22[0xC];
+       unsigned int pmcnt0_ppc_m;
+       unsigned char res23[0xC];
+       unsigned int pmcnt1_ppc_m;
+       unsigned char res24[0xC];
+       unsigned int pmcnt2_ppc_m;
+       unsigned char res25[0xC];
+       unsigned int pmcnt3_ppc_m;
+};
+
 struct exynos5_dmc {
        unsigned int concontrol;
        unsigned int memcontrol;
@@ -142,5 +251,70 @@ struct exynos5_phy_control {
        unsigned int phy_con41;
        unsigned int phy_con42;
 };
+
+enum ddr_mode {
+       DDR_MODE_DDR2,
+       DDR_MODE_DDR3,
+       DDR_MODE_LPDDR2,
+       DDR_MODE_LPDDR3,
+
+       DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+       MEM_MANUF_AUTODETECT,
+       MEM_MANUF_ELPIDA,
+       MEM_MANUF_SAMSUNG,
+
+       MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT        28
+#define CONCONTROL_RD_FETCH_SHIFT      12
+#define CONCONTROL_RD_FETCH_MASK       (0x7 << CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT       5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT       24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT   0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT    16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT       17
+#define PHY_CON0_T_WRRDCMD_MASK                (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT   11
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT        0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT       24
+#define PHY_CON12_CTRL_INC_SHIFT       16
+#define PHY_CON12_CTRL_FORCE_SHIFT     8
+#define PHY_CON12_CTRL_START_SHIFT     6
+#define PHY_CON12_CTRL_START_MASK      (1 << PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT    5
+#define PHY_CON12_CTRL_DLL_ON_MASK     (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT       1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT    24
+#define PHY_CON16_ZQ_MODE_DDS_MASK     (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK    (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK  (1 << 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT    8
+#define PHY_CON42_CTRL_BSTLEN_MASK     (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT     0
+#define PHY_CON42_CTRL_RDLAT_MASK      (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
+
 #endif
 #endif