Merge branch 'master' of git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx27 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
index ced5b2a38c20e9261ca480d4db6a38f127fbb075..92c847e44af3a6fbbcdcd49fb3f6f30d7159a8a0 100644 (file)
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -2,28 +2,14 @@
  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _IMX_REGS_H
 #define _IMX_REGS_H
 
+#include <asm/arch/regs-rtc.h>
+
 #ifndef __ASSEMBLY__
 
 extern void imx_gpio_mode (int gpio_mode);
@@ -162,29 +148,6 @@ struct gpt_regs {
 #define PORTE 4
 #define PORTF 5
 
-struct gpio_regs {
-       struct {
-               u32 ddir;
-               u32 ocr1;
-               u32 ocr2;
-               u32 iconfa1;
-               u32 iconfa2;
-               u32 iconfb1;
-               u32 iconfb2;
-               u32 dr;
-               u32 gius;
-               u32 ssr;
-               u32 icr1;
-               u32 icr2;
-               u32 imr;
-               u32 isr;
-               u32 gpr;
-               u32 swr;
-               u32 puen;
-               u32 res[0x2f];
-       } port[6];
-};
-
 /* IIM Control Registers */
 struct iim_regs {
        u32 iim_stat;
@@ -197,7 +160,7 @@ struct iim_regs {
        u32 iim_sdat;
        u32 iim_prev;
        u32 iim_srev;
-       u32 iim_prog_p;
+       u32 iim_prg_p;
        u32 iim_scs0;
        u32 iim_scs1;
        u32 iim_scs2;
@@ -206,7 +169,7 @@ struct iim_regs {
        struct fuse_bank {
                u32 fuse_regs[0x20];
                u32 fuse_rsvd[0xe0];
-       } bank[1];
+       } bank[2];
 };
 
 struct fuse_bank0_regs {
@@ -217,6 +180,8 @@ struct fuse_bank0_regs {
 
 #endif
 
+#define ARCH_MXC
+
 #define IMX_IO_BASE            0x10000000
 
 #define IMX_AIPI1_BASE         (0x00000 + IMX_IO_BASE)
@@ -224,6 +189,7 @@ struct fuse_bank0_regs {
 #define IMX_TIM1_BASE          (0x03000 + IMX_IO_BASE)
 #define IMX_TIM2_BASE          (0x04000 + IMX_IO_BASE)
 #define IMX_TIM3_BASE          (0x05000 + IMX_IO_BASE)
+#define IMX_RTC_BASE           (0x07000 + IMX_IO_BASE)
 #define UART1_BASE             (0x0a000 + IMX_IO_BASE)
 #define UART2_BASE             (0x0b000 + IMX_IO_BASE)
 #define UART3_BASE             (0x0c000 + IMX_IO_BASE)
@@ -240,11 +206,16 @@ struct fuse_bank0_regs {
 #define IMX_PLL_BASE           (0x27000 + IMX_IO_BASE)
 #define IMX_SYSTEM_CTL_BASE    (0x27800 + IMX_IO_BASE)
 #define IMX_IIM_BASE           (0x28000 + IMX_IO_BASE)
+#define IIM_BASE_ADDR          IMX_IIM_BASE
 #define IMX_FEC_BASE           (0x2b000 + IMX_IO_BASE)
 
+#define IMX_NFC_BASE           (0xD8000000)
 #define IMX_ESD_BASE           (0xD8001000)
 #define IMX_WEIM_BASE          (0xD8002000)
 
+#define NFC_BASE_ADDR          IMX_NFC_BASE
+
+
 /* FMCR System Control bit definition*/
 #define UART4_RXD_CTL  (1 << 25)
 #define UART4_RTS_CTL  (1 << 24)
@@ -471,6 +442,13 @@ struct fuse_bank0_regs {
 #define TSTAT_CAPT     (1 << 1)        /* Capture event */
 #define TSTAT_COMP     1               /* Compare event */
 
+#define GPIO1_BASE_ADDR 0x10015000
+#define GPIO2_BASE_ADDR 0x10015100
+#define GPIO3_BASE_ADDR 0x10015200
+#define GPIO4_BASE_ADDR 0x10015300
+#define GPIO5_BASE_ADDR 0x10015400
+#define GPIO6_BASE_ADDR 0x10015500
+
 #define GPIO_PIN_MASK  0x1f
 
 #define GPIO_PORT_SHIFT        5