#define GPIO2_BASE_ADDR 0x53FD0000
#define SDMA_BASE_ADDR 0x53FD4000
#define RTC_BASE_ADDR 0x53FD8000
-#define WDOG_BASE_ADDR 0x53FDC000
+#define WDOG1_BASE_ADDR 0x53FDC000
#define PWM_BASE_ADDR 0x53FE0000
#define RTIC_BASE_ADDR 0x53FEC000
#define IIM_BASE_ADDR 0x53FF0000
u32 test;
};
-/* Watchdog Timer (WDOG) registers */
-struct wdog_regs {
- u16 wcr; /* Control */
- u16 wsr; /* Service */
- u16 wrsr; /* Reset Status */
- u16 wicr; /* Interrupt Control */
- u16 wmcr; /* Misc Control */
-};
-
struct esdc_regs {
u32 esdctl0;
u32 esdcfg0;