u32 cs1cdr;
u32 cs2cdr;
u32 cdcdr; /* 0x0030 */
- u32 chscdr;
+ u32 chsccdr;
u32 cscdr2;
u32 cscdr3;
u32 cscdr4; /* 0x0040 */
#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7)
/* Define the bits in register CCDR */
-#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
+#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 21)
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
#endif
/* Define the bits in register CLPCR */
-#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
#define MXC_DPLLC_CTL_HFSM (1 << 7)
#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12)