MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx5 / crm_regs.h

diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index fcc0e36fa5a66f9c532d70f1bef51084aebe7d6e..4e0fc1bc1d69277da7b6451f05f41174cae8bdf3 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -76,6 +76,9 @@ struct mxc_ccm_reg {
        u32 CCGR4;
        u32 CCGR5;
        u32 CCGR6;      /* 0x0080 */
+#ifdef CONFIG_MX53
+       u32 CCGR7;      /* 0x0084 */
+#endif
        u32 cmeor;
 };
 
@@ -84,6 +87,9 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CACRR_ARM_PODF_MASK            0x7
 
 /* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL           (0x1 << 30)
+#define MXC_CCM_CBCDR_DDR_PODF_MASK            (0x7 << 27)
+#define MXC_CCM_CBCDR_DDR_PODF_OFFSET          27
 #define MXC_CCM_CBCDR_EMI_CLK_SEL              (0x1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL           (0x1 << 25)
 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET          22
@@ -195,7 +201,10 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCGRx */
 #define MXC_CCM_CCGR_CG_MASK                           0x3
 
+#define MXC_CCM_CCGR4_CG5_OFFSET                       10
+#define MXC_CCM_CCGR4_CG6_OFFSET                       12
 #define MXC_CCM_CCGR5_CG5_OFFSET                       10
+#define MXC_CCM_CCGR2_CG14_OFFSET                      28
 
 /* Define the bits in register CLPCR */
 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)