ARM: DRA7xx: EMIF: Change settings required for EVM board

[karo-tx-uboot.git] / arch / arm / include / asm / arch-omap4 / cpu.h

diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
index 7d5748acd4d025dbb0e59cde0bd285c091f58b0c..311c6ff522ced4ad0ad9368e9bb9b1d106dd9d46 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -115,18 +115,6 @@ struct watchdog {
 #define WD_UNLOCK1             0xAAAA
 #define WD_UNLOCK2             0x5555
 
-#define SYSCLKDIV_1            (0x1 << 6)
-#define SYSCLKDIV_2            (0x1 << 7)
-
-#define CLKSEL_GPT1            (0x1 << 0)
-
-#define EN_GPT1                        (0x1 << 0)
-#define EN_32KSYNC             (0x1 << 2)
-
-#define ST_WDT2                        (0x1 << 5)
-
-#define RESETDONE              (0x1 << 0)
-
 #define TCLR_ST                        (0x1 << 0)
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
@@ -138,8 +126,48 @@ struct watchdog {
 #define I2C_BASE1              (OMAP44XX_L4_PER_BASE + 0x70000)
 #define I2C_BASE2              (OMAP44XX_L4_PER_BASE + 0x72000)
 #define I2C_BASE3              (OMAP44XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4              (OMAP44XX_L4_PER_BASE + 0x350000)
 
 /* MUSB base */
 #define MUSB_BASE              (OMAP44XX_L4_CORE_BASE + 0xAB000)
 
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION             0x0000
+#define OMAP_GPIO_SYSCONFIG            0x0010
+#define OMAP_GPIO_SYSSTATUS            0x0114
+#define OMAP_GPIO_IRQSTATUS1           0x0118
+#define OMAP_GPIO_IRQSTATUS2           0x0128
+#define OMAP_GPIO_IRQENABLE2           0x012c
+#define OMAP_GPIO_IRQENABLE1           0x011c
+#define OMAP_GPIO_WAKE_EN              0x0120
+#define OMAP_GPIO_CTRL                 0x0130
+#define OMAP_GPIO_OE                   0x0134
+#define OMAP_GPIO_DATAIN               0x0138
+#define OMAP_GPIO_DATAOUT              0x013c
+#define OMAP_GPIO_LEVELDETECT0         0x0140
+#define OMAP_GPIO_LEVELDETECT1         0x0144
+#define OMAP_GPIO_RISINGDETECT         0x0148
+#define OMAP_GPIO_FALLINGDETECT                0x014c
+#define OMAP_GPIO_DEBOUNCE_EN          0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL         0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1      0x0160
+#define OMAP_GPIO_SETIRQENABLE1                0x0164
+#define OMAP_GPIO_CLEARWKUENA          0x0180
+#define OMAP_GPIO_SETWKUENA            0x0184
+#define OMAP_GPIO_CLEARDATAOUT         0x0190
+#define OMAP_GPIO_SETDATAOUT           0x0194
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE               0x4A306000
+#define PRM_DEVICE_BASE                (PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL            PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET      0x01
+#define PRM_RSTST              (PRM_DEVICE_BASE + 0x4)
+#define PRM_RSTST_WARM_RESET_MASK      0x07EA
+
 #endif /* _CPU_H */