Merge branch 'master' of git://git.denx.de/u-boot-video

[karo-tx-uboot.git] / arch / arm / include / asm / arch-omap4 / cpu.h

diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
index 7d8aa2092d97ecab5c9b35d169836a8c2d3b1114..3a0bfbf0c612a052296756aecceb4af72ac4b956 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -31,6 +31,51 @@
 
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
+struct gpmc_cs {
+       u32 config1;            /* 0x00 */
+       u32 config2;            /* 0x04 */
+       u32 config3;            /* 0x08 */
+       u32 config4;            /* 0x0C */
+       u32 config5;            /* 0x10 */
+       u32 config6;            /* 0x14 */
+       u32 config7;            /* 0x18 */
+       u32 nand_cmd;           /* 0x1C */
+       u32 nand_adr;           /* 0x20 */
+       u32 nand_dat;           /* 0x24 */
+       u8 res[8];              /* blow up to 0x30 byte */
+};
+
+struct gpmc {
+       u8 res1[0x10];
+       u32 sysconfig;          /* 0x10 */
+       u8 res2[0x4];
+       u32 irqstatus;          /* 0x18 */
+       u32 irqenable;          /* 0x1C */
+       u8 res3[0x20];
+       u32 timeout_control;    /* 0x40 */
+       u8 res4[0xC];
+       u32 config;             /* 0x50 */
+       u32 status;             /* 0x54 */
+       u8 res5[0x8];   /* 0x58 */
+       struct gpmc_cs cs[8];   /* 0x60, 0x90, .. */
+       u8 res6[0x14];          /* 0x1E0 */
+       u32 ecc_config;         /* 0x1F4 */
+       u32 ecc_control;        /* 0x1F8 */
+       u32 ecc_size_config;    /* 0x1FC */
+       u32 ecc1_result;        /* 0x200 */
+       u32 ecc2_result;        /* 0x204 */
+       u32 ecc3_result;        /* 0x208 */
+       u32 ecc4_result;        /* 0x20C */
+       u32 ecc5_result;        /* 0x210 */
+       u32 ecc6_result;        /* 0x214 */
+       u32 ecc7_result;        /* 0x218 */
+       u32 ecc8_result;        /* 0x21C */
+       u32 ecc9_result;        /* 0x220 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
 struct gptimer {
        u32 tidr;               /* 0x00 r */
        u8 res[0xc];
@@ -86,9 +131,55 @@ struct watchdog {
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
 
+/* GPMC BASE */
+#define GPMC_BASE              (OMAP44XX_GPMC_BASE)
+
 /* I2C base */
 #define I2C_BASE1              (OMAP44XX_L4_PER_BASE + 0x70000)
 #define I2C_BASE2              (OMAP44XX_L4_PER_BASE + 0x72000)
 #define I2C_BASE3              (OMAP44XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4              (OMAP44XX_L4_PER_BASE + 0x350000)
+
+/* MUSB base */
+#define MUSB_BASE              (OMAP44XX_L4_CORE_BASE + 0xAB000)
+
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION             0x0000
+#define OMAP_GPIO_SYSCONFIG            0x0010
+#define OMAP_GPIO_SYSSTATUS            0x0114
+#define OMAP_GPIO_IRQSTATUS1           0x0118
+#define OMAP_GPIO_IRQSTATUS2           0x0128
+#define OMAP_GPIO_IRQENABLE2           0x012c
+#define OMAP_GPIO_IRQENABLE1           0x011c
+#define OMAP_GPIO_WAKE_EN              0x0120
+#define OMAP_GPIO_CTRL                 0x0130
+#define OMAP_GPIO_OE                   0x0134
+#define OMAP_GPIO_DATAIN               0x0138
+#define OMAP_GPIO_DATAOUT              0x013c
+#define OMAP_GPIO_LEVELDETECT0         0x0140
+#define OMAP_GPIO_LEVELDETECT1         0x0144
+#define OMAP_GPIO_RISINGDETECT         0x0148
+#define OMAP_GPIO_FALLINGDETECT                0x014c
+#define OMAP_GPIO_DEBOUNCE_EN          0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL         0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1      0x0160
+#define OMAP_GPIO_SETIRQENABLE1                0x0164
+#define OMAP_GPIO_CLEARWKUENA          0x0180
+#define OMAP_GPIO_SETWKUENA            0x0184
+#define OMAP_GPIO_CLEARDATAOUT         0x0190
+#define OMAP_GPIO_SETDATAOUT           0x0194
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE               0x4A306000
+#define PRM_DEVICE_BASE                (PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL            PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET      0x01
+#define PRM_RSTST              (PRM_DEVICE_BASE + 0x4)
+#define PRM_RSTST_WARM_RESET_MASK      0x07EA
 
 #endif /* _CPU_H */