/* GPMC */
#define OMAP44XX_GPMC_BASE 0x50000000
-/* DMM */
-#define OMAP44XX_DMM_BASE 0x4E000000
-#define DMM_LISA_MAP_BASE (OMAP44XX_DMM_BASE + 0x40)
-#define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20)
-#define DMM_LISA_MAP_SYS_SIZE_SHIFT 20
-#define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24)
/*
* Hardware Register Details
*/
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
/* SRAM scratch space entries */
#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
+#define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF