u32 acgr; /*0x1024*/
};
+/*
+ * Application Power Management (APMU) Registers
+ * Refer Register Datasheet 9.2
+ */
+struct panthapmu_registers {
+ u8 pad0[0x0054];
+ u32 sd1; /*0x0054*/
+ u8 pad1[0x00e0 - 0x054 - 4];
+ u32 sd3; /*0x00e0*/
+};
+
/*
* APB Clock Reset/Control Registers
* Refer Register Datasheet 6.14
*/
u32 panth_sdram_base(int);
u32 panth_sdram_size(int);
+int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
#endif /* _PANTHEON_CPU_H */