/*
* Peripheral memory map
*/
+#define STM32_SYSMEM_BASE 0x1FFF0000
#define STM32_PERIPH_BASE 0x40000000
#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000)
#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
/*
* Register maps
*/
+struct stm32_u_id_regs {
+ u32 u_id_low;
+ u32 u_id_mid;
+ u32 u_id_high;
+};
+
struct stm32_rcc_regs {
u32 cr; /* RCC clock control */
u32 pllcfgr; /* RCC PLL configuration */
/*
* Registers access macros
*/
+#define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10)
+#define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE)
+
#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800)
#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)