Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[karo-tx-uboot.git] / arch / arm / include / asm / arch-sunxi / clock_sun6i.h

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 3d4fcd143fc7a377c890fd6a46dff67403d84bee..4711260c1eef58196d40c46f856c3805012a2824 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -173,7 +173,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL1_CTRL_M(n)             ((((n) - 1) & 0x3) << 0)
 #define CCM_PLL1_CTRL_K(n)             ((((n) - 1) & 0x3) << 4)
 #define CCM_PLL1_CTRL_N(n)             ((((n) - 1) & 0x1f) << 8)
-#define CCM_PLL1_CTRL_MAGIC            (0x1 << 16)
+#define CCM_PLL1_CTRL_P(n)             (((n) & 0x3) << 16)
 #define CCM_PLL1_CTRL_EN               (0x1 << 31)
 
 #define CCM_PLL3_CTRL_M(n)             ((((n) - 1) & 0xf) << 0)
@@ -185,6 +185,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL5_CTRL_K(n)             ((((n) - 1) & 0x3) << 4)
 #define CCM_PLL5_CTRL_N(n)             ((((n) - 1) & 0x1f) << 8)
 #define CCM_PLL5_CTRL_UPD              (0x1 << 20)
+#define CCM_PLL5_CTRL_SIGMA_DELTA_EN   (0x1 << 24)
 #define CCM_PLL5_CTRL_EN               (0x1 << 31)
 
 #define PLL6_CFG_DEFAULT               0x90041811 /* 600 MHz */
@@ -203,6 +204,7 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB_OHCI0      29
 #define AHB_GATE_OFFSET_USB_EHCI1      27
 #define AHB_GATE_OFFSET_USB_EHCI0      26
+#define AHB_GATE_OFFSET_USB0           24
 #define AHB_GATE_OFFSET_MCTL           14
 #define AHB_GATE_OFFSET_GMAC           17
 #define AHB_GATE_OFFSET_MMC3           11
@@ -227,10 +229,12 @@ struct sunxi_ccm_reg {
 #define CCM_MMC_CTRL_PLL6              (0x1 << 24)
 #define CCM_MMC_CTRL_ENABLE            (0x1 << 31)
 
+#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
 /* There is no global phy clk gate on sun6i, define as 0 */
 #define CCM_USB_CTRL_PHYGATE 0
+#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
 #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
 
@@ -254,6 +258,8 @@ struct sunxi_ccm_reg {
 #define CCM_LCD_CH0_CTRL_PLL3_2X       (2 << 24)
 #define CCM_LCD_CH0_CTRL_PLL7_2X       (3 << 24)
 #define CCM_LCD_CH0_CTRL_MIPI_PLL      (4 << 24)
+/* No reset bit in ch0_clk_cfg (reset is controlled through ahb_reset1) */
+#define CCM_LCD_CH0_CTRL_RST           0
 #define CCM_LCD_CH0_CTRL_GATE          (0x1 << 31)
 
 #define CCM_LCD_CH1_CTRL_M(n)          ((((n) - 1) & 0xf) << 0)
@@ -272,7 +278,13 @@ struct sunxi_ccm_reg {
 #define CCM_HDMI_CTRL_DDC_GATE         (0x1 << 30)
 #define CCM_HDMI_CTRL_GATE             (0x1 << 31)
 
+#ifndef CONFIG_MACH_SUN8I
 #define MBUS_CLK_DEFAULT               0x81000001 /* PLL6 / 2 */
+#else
+#define MBUS_CLK_DEFAULT               0x81000003 /* PLL6 / 4 */
+#endif
+
+#define CCM_PLL5_PATTERN               0xd1303333
 
 /* ahb_reset0 offsets */
 #define AHB_RESET_OFFSET_GMAC          17
@@ -308,4 +320,6 @@ struct sunxi_ccm_reg {
 #define CCM_DE_CTRL_PLL10              (5 << 24)
 #define CCM_DE_CTRL_GATE               (1 << 31)
 
+void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
+
 #endif /* _SUNXI_CLOCK_SUN6I_H */