ARM: tegra: pinmux: move some type definitions

[karo-tx-uboot.git] / arch / arm / include / asm / arch-tegra / pinmux.h

diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index 035159d665371fa6100bebf6ed60eea8c5ff65eb..1562fa410c42c8350507c9cfae64497c73bf9c8d 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -23,39 +23,74 @@ enum pmux_tristate {
        PMUX_TRI_TRISTATE = 1,
 };
 
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 enum pmux_pin_io {
        PMUX_PIN_OUTPUT = 0,
        PMUX_PIN_INPUT = 1,
        PMUX_PIN_NONE,
 };
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
 enum pmux_pin_lock {
        PMUX_PIN_LOCK_DEFAULT = 0,
        PMUX_PIN_LOCK_DISABLE,
        PMUX_PIN_LOCK_ENABLE,
 };
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_OD
 enum pmux_pin_od {
        PMUX_PIN_OD_DEFAULT = 0,
        PMUX_PIN_OD_DISABLE,
        PMUX_PIN_OD_ENABLE,
 };
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 enum pmux_pin_ioreset {
        PMUX_PIN_IO_RESET_DEFAULT = 0,
        PMUX_PIN_IO_RESET_DISABLE,
        PMUX_PIN_IO_RESET_ENABLE,
 };
+#endif
 
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 enum pmux_pin_rcv_sel {
        PMUX_PIN_RCV_SEL_DEFAULT = 0,
        PMUX_PIN_RCV_SEL_NORMAL,
        PMUX_PIN_RCV_SEL_HIGH,
 };
-#endif /* TEGRA_PMX_HAS_RCV_SEL */
-#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+#endif
+
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
+/* Defines a pin group cfg's low-power mode select */
+enum pmux_lpmd {
+       PMUX_LPMD_X8 = 0,
+       PMUX_LPMD_X4,
+       PMUX_LPMD_X2,
+       PMUX_LPMD_X,
+       PMUX_LPMD_NONE = -1,
+};
+#endif
+
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pmux_schmt {
+       PMUX_SCHMT_DISABLE = 0,
+       PMUX_SCHMT_ENABLE = 1,
+       PMUX_SCHMT_NONE = -1,
+};
+#endif
+
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pmux_hsm {
+       PMUX_HSM_DISABLE = 0,
+       PMUX_HSM_ENABLE = 1,
+       PMUX_HSM_NONE = -1,
+};
+#endif
 
 /*
  * This defines the configuration for a pin, including the function assigned,
@@ -68,18 +103,30 @@ struct pmux_pingrp_config {
        u32 func:8;             /* function to assign PMUX_FUNC_... */
        u32 pull:2;             /* pull up/down/normal PMUX_PULL_...*/
        u32 tristate:2;         /* tristate or normal PMUX_TRI_...  */
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
        u32 io:2;               /* input or output PMUX_PIN_...     */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
        u32 lock:2;             /* lock enable/disable PMUX_PIN...  */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_OD
        u32 od:2;               /* open-drain or push-pull driver   */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
        u32 ioreset:2;          /* input/output reset PMUX_PIN...   */
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
        u32 rcv_sel:2;          /* select between High and Normal  */
                                /* VIL/VIH receivers */
 #endif
-#endif
 };
 
+#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
+/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
+void pinmux_set_tristate_input_clamping(void);
+void pinmux_clear_tristate_input_clamping(void);
+#endif
+
 /* Set the mux function for a pin group */
 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
 
@@ -92,7 +139,7 @@ void pinmux_tristate_enable(enum pmux_pingrp pin);
 /* Set a pin group to normal (non tristate) */
 void pinmux_tristate_disable(enum pmux_pingrp pin);
 
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 /* Set a pin group as input or output */
 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
 #endif
@@ -106,7 +153,7 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
                                int len);
 
-#ifdef TEGRA_PMX_HAS_DRVGRPS
+#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
 
 #define PMUX_SLWF_MIN  0
 #define PMUX_SLWF_MAX  3
@@ -124,29 +171,6 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 #define PMUX_DRVDN_MAX 127
 #define PMUX_DRVDN_NONE        -1
 
-/* Defines a pin group cfg's low-power mode select */
-enum pmux_lpmd {
-       PMUX_LPMD_X8 = 0,
-       PMUX_LPMD_X4,
-       PMUX_LPMD_X2,
-       PMUX_LPMD_X,
-       PMUX_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pmux_schmt {
-       PMUX_SCHMT_DISABLE = 0,
-       PMUX_SCHMT_ENABLE = 1,
-       PMUX_SCHMT_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pmux_hsm {
-       PMUX_HSM_DISABLE = 0,
-       PMUX_HSM_ENABLE = 1,
-       PMUX_HSM_NONE = -1,
-};
-
 /*
  * This defines the configuration for a pin group's pad control config
  */
@@ -156,9 +180,15 @@ struct pmux_drvgrp_config {
        u32 slwr:3;             /* rising edge slew          */
        u32 drvup:8;            /* pull-up drive strength    */
        u32 drvdn:8;            /* pull-down drive strength  */
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
        u32 lpmd:3;             /* low-power mode selection  */
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
        u32 schmt:2;            /* schmidt enable            */
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
        u32 hsm:2;              /* high-speed mode enable    */
+#endif
 };
 
 /**
@@ -170,7 +200,7 @@ struct pmux_drvgrp_config {
 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
                                int len);
 
-#endif /* TEGRA_PMX_HAS_DRVGRPS */
+#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
 
 struct pmux_pingrp_desc {
        u8 funcs[4];