zynq: Provide a framework to read clock frequencies

[karo-tx-uboot.git] / arch / arm / include / asm / arch-zynq / hardware.h

diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index d0fba64283945210f2e033056ddac0d423e5bc70..39184da40ea02530bcced9d9223f961512b92537 100644 (file)
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -34,12 +34,40 @@ struct slcr_regs {
        u32 scl; /* 0x0 */
        u32 slcr_lock; /* 0x4 */
        u32 slcr_unlock; /* 0x8 */
-       u32 reserved0[75];
+       u32 reserved0_1[61];
+       u32 arm_pll_ctrl; /* 0x100 */
+       u32 ddr_pll_ctrl; /* 0x104 */
+       u32 io_pll_ctrl; /* 0x108 */
+       u32 reserved0_2[5];
+       u32 arm_clk_ctrl; /* 0x120 */
+       u32 ddr_clk_ctrl; /* 0x124 */
+       u32 dci_clk_ctrl; /* 0x128 */
+       u32 aper_clk_ctrl; /* 0x12c */
+       u32 reserved0_3[2];
        u32 gem0_rclk_ctrl; /* 0x138 */
        u32 gem1_rclk_ctrl; /* 0x13c */
        u32 gem0_clk_ctrl; /* 0x140 */
        u32 gem1_clk_ctrl; /* 0x144 */
-       u32 reserved1[46];
+       u32 smc_clk_ctrl; /* 0x148 */
+       u32 lqspi_clk_ctrl; /* 0x14c */
+       u32 sdio_clk_ctrl; /* 0x150 */
+       u32 uart_clk_ctrl; /* 0x154 */
+       u32 spi_clk_ctrl; /* 0x158 */
+       u32 can_clk_ctrl; /* 0x15c */
+       u32 can_mioclk_ctrl; /* 0x160 */
+       u32 dbg_clk_ctrl; /* 0x164 */
+       u32 pcap_clk_ctrl; /* 0x168 */
+       u32 reserved0_4[1];
+       u32 fpga0_clk_ctrl; /* 0x170 */
+       u32 reserved0_5[3];
+       u32 fpga1_clk_ctrl; /* 0x180 */
+       u32 reserved0_6[3];
+       u32 fpga2_clk_ctrl; /* 0x190 */
+       u32 reserved0_7[3];
+       u32 fpga3_clk_ctrl; /* 0x1a0 */
+       u32 reserved0_8[8];
+       u32 clk_621_true; /* 0x1c4 */
+       u32 reserved1[14];
        u32 pss_rst_ctrl; /* 0x200 */
        u32 reserved2[15];
        u32 fpga_rst_ctrl; /* 0x240 */