ARM: OMAP3xxx: hwmod: Convert SHAM crypto device data to hwmod

[karo-tx-linux.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index ac7e03ec952f22f7c856084c15e2de3e767e4273..f01fe0795e69f0659109e48b24c17b976221dba5 100644 (file)
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3545,6 +3545,71 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
+static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
+       .sidle_shift    = 4,
+       .srst_shift     = 1,
+       .autoidle_shift = 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
+       .rev_offs       = 0x5c,
+       .sysc_offs      = 0x60,
+       .syss_offs      = 0x64,
+       .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+       .sysc_fields    = &omap3_sham_sysc_fields,
+};
+
+static struct omap_hwmod_class omap3xxx_sham_class = {
+       .name   = "sham",
+       .sysc   = &omap3_sham_sysc,
+};
+
+static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
+       { .irq = 49 + OMAP_INTC_START, },
+       { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
+       { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
+       { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap3xxx_sham_hwmod = {
+       .name           = "sham",
+       .mpu_irqs       = omap3_sham_mpu_irqs,
+       .sdma_reqs      = omap3_sham_sdma_reqs,
+       .main_clk       = "sha12_ick",
+       .prcm           = {
+               .omap2 = {
+                       .module_offs = CORE_MOD,
+                       .prcm_reg_id = 1,
+                       .module_bit = OMAP3430_EN_SHA12_SHIFT,
+                       .idlest_reg_id = 1,
+                       .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
+               },
+       },
+       .class          = &omap3xxx_sham_class,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
+       {
+               .pa_start       = 0x480c3000,
+               .pa_end         = 0x480c3000 + 0x64 - 1,
+               .flags          = ADDR_TYPE_RT
+       },
+       { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
+       .master         = &omap3xxx_l4_core_hwmod,
+       .slave          = &omap3xxx_sham_hwmod,
+       .clk            = "sha12_ick",
+       .addr           = omap3xxx_sham_addrs,
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
        &omap3xxx_l3_main__l4_core,
        &omap3xxx_l3_main__l4_per,
@@ -3596,8 +3661,28 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
 };
 
 /* GP-only hwmod links */
-static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
+static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
+       &omap3xxx_l4_sec__timer12,
+       &omap3xxx_l4_core__sham,
+       NULL
+};
+
+static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
        &omap3xxx_l4_sec__timer12,
+       &omap3xxx_l4_core__sham,
+       NULL
+};
+
+static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
+       &omap3xxx_l4_sec__timer12,
+       /*
+        * Apparently the SHA/MD5 accelerator IP block is only present
+        * on some AM35xx chips, and no one knows which ones.  See
+        * http://www.spinics.net/lists/arm-kernel/msg215466.html So
+        * if you need this IP block on an AM35xx, try uncommenting
+        * the next line.
+        */
+       /* &omap3xxx_l4_core__sham, */
        NULL
 };
 
@@ -3704,7 +3789,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
 int __init omap3xxx_hwmod_init(void)
 {
        int r;
-       struct omap_hwmod_ocp_if **h = NULL;
+       struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
        unsigned int rev;
 
        omap_hwmod_init();
@@ -3714,13 +3799,6 @@ int __init omap3xxx_hwmod_init(void)
        if (r < 0)
                return r;
 
-       /* Register GP-only hwmod links. */
-       if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
-               r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
-               if (r < 0)
-                       return r;
-       }
-
        rev = omap_rev();
 
        /*
@@ -3732,11 +3810,14 @@ int __init omap3xxx_hwmod_init(void)
            rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
            rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
                h = omap34xx_hwmod_ocp_ifs;
+               h_gp = omap34xx_gp_hwmod_ocp_ifs;
        } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
                h = am35xx_hwmod_ocp_ifs;
+               h_gp = am35xx_gp_hwmod_ocp_ifs;
        } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
                   rev == OMAP3630_REV_ES1_2) {
                h = omap36xx_hwmod_ocp_ifs;
+               h_gp = omap36xx_gp_hwmod_ocp_ifs;
        } else {
                WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
                return -EINVAL;
@@ -3746,6 +3827,14 @@ int __init omap3xxx_hwmod_init(void)
        if (r < 0)
                return r;
 
+       /* Register GP-only hwmod links. */
+       if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
+               r = omap_hwmod_register_links(h_gp);
+               if (r < 0)
+                       return r;
+       }
+
+
        /*
         * Register hwmod links specific to certain ES levels of a
         * particular family of silicon (e.g., 34xx ES1.0)