return -ENODEV;
if (!atomic_inc_not_zero(&active_events)) {
- if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
- atomic_dec(&active_events);
- return -EINVAL;
- }
-
mutex_lock(&pmu_reserve_mutex);
if (atomic_read(&active_events) == 0)
err = mipspmu_get_irq();
if (err)
return err;
- err = __hw_perf_event_init(event);
- if (err)
- hw_perf_event_destroy(event);
-
- return err;
+ return __hw_perf_event_init(event);
}
static struct pmu pmu = {
}
-static int validate_event(struct cpu_hw_events *cpuc,
- struct perf_event *event)
-{
- struct hw_perf_event fake_hwc = event->hw;
-
- /* Allow mixed event group. So return 1 to pass validation. */
- if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
- return 1;
-
- return mipsxx_pmu_alloc_counter(cpuc, &fake_hwc) >= 0;
-}
-
static int validate_group(struct perf_event *event)
{
struct perf_event *sibling, *leader = event->group_leader;
memset(&fake_cpuc, 0, sizeof(fake_cpuc));
- if (!validate_event(&fake_cpuc, leader))
+ if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
return -EINVAL;
list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
- if (!validate_event(&fake_cpuc, sibling))
+ if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
return -EINVAL;
}
- if (!validate_event(&fake_cpuc, event))
+ if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
return -EINVAL;
return 0;
}
err = 0;
- if (event->group_leader != event) {
+ if (event->group_leader != event)
err = validate_group(event);
- if (err)
- return -EINVAL;
- }
event->destroy = hw_perf_event_destroy;
+
+ if (err)
+ event->destroy(event);
+
return err;
}
}
/* 24K */
-#define IS_UNSUPPORTED_24K_EVENT(r, b) \
- ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 || \
- (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 || \
- (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 || \
- (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) || \
- ((b) >= 68 && (b) <= 127))
#define IS_BOTH_COUNTERS_24K_EVENT(b) \
((b) == 0 || (b) == 1 || (b) == 11)
/* 34K */
-#define IS_UNSUPPORTED_34K_EVENT(r, b) \
- ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 || \
- (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) || \
- ((b) >= 68 && (b) <= 127))
#define IS_BOTH_COUNTERS_34K_EVENT(b) \
((b) == 0 || (b) == 1 || (b) == 11)
#ifdef CONFIG_MIPS_MT_SMP
#endif
/* 74K */
-#define IS_UNSUPPORTED_74K_EVENT(r, b) \
- ((r) == 5 || ((r) >= 135 && (r) <= 137) || \
- ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 || \
- (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) || \
- (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 || \
- (b) == 61 || (r) == 62 || (r) == 191 || \
- ((b) >= 64 && (b) <= 127))
#define IS_BOTH_COUNTERS_74K_EVENT(b) \
((b) == 0 || (b) == 1)
/* 1004K */
-#define IS_UNSUPPORTED_1004K_EVENT(r, b) \
- ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 38 || \
- (r) == 175 || (b) == 63 || ((b) >= 68 && (b) <= 127))
#define IS_BOTH_COUNTERS_1004K_EVENT(b) \
((b) == 0 || (b) == 1 || (b) == 11)
#ifdef CONFIG_MIPS_MT_SMP
unsigned int raw_id = config & 0xff;
unsigned int base_id = raw_id & 0x7f;
+ raw_event.event_id = base_id;
+
switch (current_cpu_type()) {
case CPU_24K:
- if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id))
- return ERR_PTR(-EOPNOTSUPP);
- raw_event.event_id = base_id;
if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
else
#endif
break;
case CPU_34K:
- if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id))
- return ERR_PTR(-EOPNOTSUPP);
- raw_event.event_id = base_id;
if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
else
#endif
break;
case CPU_74K:
- if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id))
- return ERR_PTR(-EOPNOTSUPP);
- raw_event.event_id = base_id;
if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
else
#endif
break;
case CPU_1004K:
- if (IS_UNSUPPORTED_1004K_EVENT(raw_id, base_id))
- return ERR_PTR(-EOPNOTSUPP);
- raw_event.event_id = base_id;
if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
else