powerpc/85xx: add support for FM2 DTSEC5

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / fsl_corenet_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 4307a4ccbb5349074b2352ef1fa43dcd0ae17c72..8aac1dec0f2e2c27a4391c88f5e1c25694fc7478 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -68,6 +68,7 @@ static const char *serdes_prtcl_str[] = {
        [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
        [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
        [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
+       [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
        [XAUI_FM1] = "XAUI_FM1",
        [XAUI_FM2] = "XAUI_FM2",
        [AURORA] = "DEBUG",
@@ -482,13 +483,19 @@ static void wait_for_rstdone(unsigned int bank)
                printf("SERDES: timeout resetting bank %u\n", bank + 1);
 }
 
+
+void __soc_serdes_init(void)
+{
+       /* Allow for SoC-specific initialization in <SOC>_serdes.c  */
+};
+void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
+
 void fsl_serdes_init(void)
 {
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        int cfg;
        serdes_corenet_t *srds_regs;
        int lane, bank, idx;
-       enum srds_prtcl lane_prtcl;
        int have_bank[SRDS_MAX_BANK] = {};
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
        u32 serdes8_devdisr = 0;
@@ -497,12 +504,10 @@ void fsl_serdes_init(void)
        const char *srds_lpd_arg;
        size_t arglen;
 #endif
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
-       enum srds_prtcl device;
-#endif
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
        int need_serdes_a001;   /* TRUE == need work-around for SERDES A001 */
 #endif
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
        char buffer[HWCONFIG_BUFFER_SIZE];
        char *buf = NULL;
 
@@ -512,6 +517,7 @@ void fsl_serdes_init(void)
         */
        if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
                buf = buffer;
+#endif
 
        /* Is serdes enabled at all? */
        if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
@@ -570,6 +576,8 @@ void fsl_serdes_init(void)
                }
        }
 
+       soc_serdes_init();
+
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
        /*
         * Bank two uses the clock from bank three, so if bank two is enabled,
@@ -611,7 +619,10 @@ void fsl_serdes_init(void)
                }
        }
 
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
        for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+               enum srds_prtcl lane_prtcl;
+
                idx = serdes_get_lane_idx(lane);
                lane_prtcl = serdes_get_prtcl(cfg, lane);
 
@@ -648,6 +659,7 @@ void fsl_serdes_init(void)
                case SGMII_FM2_DTSEC2:
                case SGMII_FM2_DTSEC3:
                case SGMII_FM2_DTSEC4:
+               case SGMII_FM2_DTSEC5:
                case XAUI_FM1:
                case XAUI_FM2:
                case SRIO1:
@@ -707,6 +719,10 @@ void fsl_serdes_init(void)
                        serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
                                            FSL_CORENET_DEVDISR2_DTSEC2_4;
                        break;
+               case SGMII_FM2_DTSEC5:
+                       serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
+                                           FSL_CORENET_DEVDISR2_DTSEC2_5;
+                       break;
                case XAUI_FM1:
                        serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1    |
                                            FSL_CORENET_DEVDISR2_10GEC1;
@@ -723,6 +739,7 @@ void fsl_serdes_init(void)
 
 #endif
        }
+#endif
 
 #ifdef DEBUG
        puts("\n");
@@ -778,11 +795,4 @@ void fsl_serdes_init(void)
                             SRDS_RSTCTL_SDPD);
        }
 #endif
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
-       for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
-               if (is_serdes_configured(device))
-                       __serdes_reset_rx(srds_regs, cfg, device);
-       }
-#endif
 }