powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc8xxx / ddr / main.c

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index b47268c20eacc22e31fe1314e3c18999b24ab9e4..2885906e875c6498136f9c6be35c9d1d38193655 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -526,6 +526,17 @@ phys_size_t fsl_ddr_sdram(void)
 #endif
                total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
 
+       /* setup 3-way interleaving before enabling DDRC */
+       switch (info.memctl_opts[0].memctl_interleaving_mode) {
+       case FSL_DDR_3WAY_1KB_INTERLEAVING:
+       case FSL_DDR_3WAY_4KB_INTERLEAVING:
+       case FSL_DDR_3WAY_8KB_INTERLEAVING:
+               fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode);
+               break;
+       default:
+               break;
+       }
+
        /* Program configuration registers. */
        for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
                debug("Programming controller %u\n", i);
@@ -561,7 +572,6 @@ phys_size_t fsl_ddr_sdram(void)
                        case FSL_DDR_3WAY_8KB_INTERLEAVING:
                                law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
                                if (i == 0) {
-                                       fsl_ddr_set_intl3r(info.memctl_opts[i].memctl_interleaving_mode);
                                        fsl_ddr_set_lawbar(&info.common_timing_params[i],
                                                law_memctl, i);
                                }