powerpc/85xx: add T4080 SoC support

[karo-tx-uboot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 741b8618d11fbd25ffd99e6658b95e122f5e72cf..eff573b5aded3c83b75dc83083aa46bc60897b98 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1748,7 +1748,8 @@ typedef struct ccsr_gur {
 /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT      8
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK    0x3f
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+       defined(CONFIG_PPC_T4080)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xfc000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  26
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL                0x00fe0000
@@ -1848,7 +1849,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
 #endif
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+       defined(CONFIG_PPC_T4080)
 #define FSL_CORENET_RCWSR13_EC1                        0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII       0x00000000
 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO               0x40000000