powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3

[karo-tx-uboot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index f85cee270fcaecdbde743f02973dc5277d1e09da..1bbf9867af53849edcab25e0db8d547d6f77c579 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1700,12 +1700,24 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1         0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2         0x00100000
 #define FSL_CORENET_RCWSR11_EC1                        0x00c00000 /* bits 360..361 */
-#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1     0x00000000
-#define FSL_CORENET_RCWSR11_EC1_FM1_USB1       0x00800000
+#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1             0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_USB1               0x00800000
 #define FSL_CORENET_RCWSR11_EC2                        0x001c0000 /* bits 363..365 */
-#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1     0x00000000
-#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2     0x00080000
-#define FSL_CORENET_RCWSR11_EC2_USB2           0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1             0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2             0x00080000
+#define FSL_CORENET_RCWSR11_EC2_USB2                   0x00100000
+#endif
+#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \
+       || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII       0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII         0x00800000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE                0x00c00000
+#define FSL_CORENET_RCWSR11_EC2                        0x00180000 /* bits 363..364 */
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII       0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII         0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE                0x00180000
+#endif
        u8      res18[192];
        u32     scratchrw[4];   /* Scratch Read/Write */
        u8      res19[240];
@@ -1759,7 +1771,8 @@ typedef struct ccsr_gur {
        u32     cgencrl;        /* Core general control */
        u8      res31[184];
        u32     sriopstecr;     /* SRIO prescaler timer enable control */
-       u8      res32[1788];
+       u32     dcsrcr;         /* DCSR Control register */
+       u8      res32[1784];
        u32     pmuxcr;         /* Pin multiplexing control */
        u8      res33[60];
        u32     iovselsr;       /* I/O voltage selection status */
@@ -1772,6 +1785,10 @@ typedef struct ccsr_gur {
        u8      res37[380];
 } ccsr_gur_t;
 
+#define FSL_CORENET_DCSR_SZ_MASK       0x00000003
+#define FSL_CORENET_DCSR_SZ_4M         0x0
+#define FSL_CORENET_DCSR_SZ_1G         0x3
+
 /*
  * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
  * everything after has RMan thus msg unit LIODN is used for maintenance
@@ -1868,6 +1885,7 @@ typedef struct ccsr_gur {
 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
 #define MPC85xx_PORDEVSR_SGMII1_DIS    0x10000000
 #define MPC85xx_PORDEVSR_SGMII2_DIS    0x08000000
+#define MPC85xx_PORDEVSR_TSEC1_PRTC    0x02000000
 #else
 #define MPC85xx_PORDEVSR_SGMII1_DIS    0x20000000
 #define MPC85xx_PORDEVSR_SGMII2_DIS    0x10000000
@@ -1906,7 +1924,12 @@ typedef struct ccsr_gur {
        u8      res1[8];
        u32     gpporcr;        /* General-purpose POR configuration */
        u8      res2[12];
+#if defined(CONFIG_MPC8536)
+       u32     gencfgr;        /* General Configuration Register */
+#define MPC85xx_GENCFGR_SDHC_WP_INV    0x20000000
+#else
        u32     gpiocr;         /* GPIO control */
+#endif
        u8      res3[12];
 #if defined(CONFIG_MPC8569)
        u32     plppar1;        /* Platform port pin assignment 1 */
@@ -1966,6 +1989,9 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_CAN2_TDM                        0x00000002
 #define MPC85xx_PMUXCR_CAN2_RES                        0x00000003
 #endif
+#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#define MPC85xx_PMUXCR_TSEC1_1         0x10000000
+#else
 #define MPC85xx_PMUXCR_SD_DATA         0x80000000
 #define MPC85xx_PMUXCR_SDHC_CD         0x40000000
 #define MPC85xx_PMUXCR_SDHC_WP         0x20000000
@@ -1984,6 +2010,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_QE10            0x00000020
 #define MPC85xx_PMUXCR_QE11            0x00000010
 #define MPC85xx_PMUXCR_QE12            0x00000008
+#endif
 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
 #define MPC85xx_PMUXCR_TDM_MASK                0x0001cc00
 #define MPC85xx_PMUXCR_TDM             0x00014800
@@ -2017,7 +2044,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE                0x00001000
 #endif
 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
-#define MPC85xx_PMUXCR2_ETSECUSB_MASK  0x001f1000
+#define MPC85xx_PMUXCR2_ETSECUSB_MASK  0x001f8000
 #define MPC85xx_PMUXCR2_USB            0x00150000
 #endif
        u8      res6[8];
@@ -2296,6 +2323,22 @@ typedef struct ccsr_usb_phy {
 } ccsr_usb_phy_t;
 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
 
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+struct ccsr_raide {
+       u8      res0[0x543];
+       u32     liodnbr;                        /* LIODN Base Register */
+       u8      res1[0xab8];
+       struct {
+               struct {
+                       u32     cfg0;           /* cfg register 0 */
+                       u32     cfg1;           /* cfg register 1 */
+                       u8      res1[0x3f8];
+               } ring[2];
+               u8      res[0x800];
+       } jq[2];
+};
+#endif
+
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET      0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET          0x8000
@@ -2326,6 +2369,7 @@ typedef struct ccsr_usb_phy {
 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET      0x316000
 #define CONFIG_SYS_FSL_QMAN_OFFSET             0x318000
 #define CONFIG_SYS_FSL_BMAN_OFFSET             0x31a000
+#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET      0x320000
 #define CONFIG_SYS_FSL_FM1_OFFSET              0x400000
 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET       0x488000
 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET       0x489000
@@ -2374,6 +2418,8 @@ typedef struct ccsr_usb_phy {
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET                0x2e000
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET      0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET      0xE3000
+#define CONFIG_SYS_SNVS_OFFSET                 0xE6000
+#define CONFIG_SYS_SFP_OFFSET                  0xE7000
 #define CONFIG_SYS_MPC85xx_CPM_OFFSET          0x80000
 #define CONFIG_SYS_FSL_QMAN_OFFSET             0x88000
 #define CONFIG_SYS_FSL_BMAN_OFFSET             0x8a000
@@ -2394,6 +2440,8 @@ typedef struct ccsr_usb_phy {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \