powerpc/perf: Add support for SIER

[karo-tx-linux.git] / arch / powerpc / include / asm / reg.h

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index c9c67fc888c93d229b23a617d0fd9c2aa7a71e79..5c6fbe2c5ce6e3192152e379eb4cdcd9e9c89912 100644 (file)
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -268,6 +268,13 @@
 #define SPRN_FSCR      0x099   /* Facility Status & Control Register */
 #define   FSCR_TAR     (1 << (63-55)) /* Enable Target Address Register */
 #define   FSCR_DSCR    (1 << (63-61)) /* Enable Data Stream Control Register */
+#define SPRN_HFSCR     0xbe    /* HV=1 Facility Status & Control Register */
+#define   HFSCR_TAR    (1 << (63-55)) /* Enable Target Address Register */
+#define   HFSCR_TM     (1 << (63-58)) /* Enable Transactional Memory */
+#define   HFSCR_PM     (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */
+#define   HFSCR_DSCR   (1 << (63-61)) /* Enable Data Stream Control Register */
+#define   HFSCR_VECVSX (1 << (63-62)) /* Enable VMX/VSX  */
+#define   HFSCR_FP     (1 << (63-63)) /* Enable Floating Point */
 #define SPRN_TAR       0x32f   /* Target Address Register */
 #define SPRN_LPCR      0x13E   /* LPAR Control Register */
 #define   LPCR_VPM0    (1ul << (63-0))
@@ -631,6 +638,7 @@
 #define   MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
 #define   MMCR0_FCHV   0x00000001UL /* freeze conditions in hypervisor mode */
 #define SPRN_MMCR1     798
+#define SPRN_MMCR2     769
 #define SPRN_MMCRA     0x312
 #define   MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
 #define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
@@ -649,6 +657,10 @@
 #define   POWER7P_MMCRA_SIAR_VALID 0x10000000  /* P7+ SIAR contents valid */
 #define   POWER7P_MMCRA_SDAR_VALID 0x08000000  /* P7+ SDAR contents valid */
 
+#define SPRN_MMCRH     316     /* Hypervisor monitor mode control register */
+#define SPRN_MMCRS     894     /* Supervisor monitor mode control register */
+#define SPRN_MMCRC     851     /* Core monitor mode control register */
+
 #define SPRN_PMC1      787
 #define SPRN_PMC2      788
 #define SPRN_PMC3      789
@@ -659,6 +671,11 @@
 #define SPRN_PMC8      794
 #define SPRN_SIAR      780
 #define SPRN_SDAR      781
+#define SPRN_SIER      784
+#define   SIER_SIPR            0x2000000       /* Sampled MSR_PR */
+#define   SIER_SIHV            0x1000000       /* Sampled MSR_HV */
+#define   SIER_SIAR_VALID      0x0400000       /* SIAR contents valid */
+#define   SIER_SDAR_VALID      0x0200000       /* SDAR contents valid */
 
 #define SPRN_PA6T_MMCR0 795
 #define   PA6T_MMCR0_EN0       0x0000000000000001UL