Merge tag 'staging-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...

[karo-tx-linux.git] / arch / powerpc / kvm / book3s_hv_builtin.c

diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c
index b739ff80e979b8564ecc11524e46edb981f200a9..9c71c72e65ce8153d5816d2a75e68285d3d53997 100644 (file)
--- a/arch/powerpc/kvm/book3s_hv_builtin.c
+++ b/arch/powerpc/kvm/book3s_hv_builtin.c
@@ -23,6 +23,7 @@
 #include <asm/kvm_book3s.h>
 #include <asm/archrandom.h>
 #include <asm/xics.h>
+#include <asm/xive.h>
 #include <asm/dbell.h>
 #include <asm/cputhreads.h>
 #include <asm/io.h>
@@ -194,12 +195,6 @@ long kvmppc_h_random(struct kvm_vcpu *vcpu)
        return H_HARDWARE;
 }
 
-static inline void rm_writeb(unsigned long paddr, u8 val)
-{
-       __asm__ __volatile__("stbcix %0,0,%1"
-               : : "r" (val), "r" (paddr) : "memory");
-}
-
 /*
  * Send an interrupt or message to another CPU.
  * The caller needs to include any barrier needed to order writes
@@ -207,7 +202,7 @@ static inline void rm_writeb(unsigned long paddr, u8 val)
  */
 void kvmhv_rm_send_ipi(int cpu)
 {
-       unsigned long xics_phys;
+       void __iomem *xics_phys;
        unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER);
 
        /* On POWER9 we can use msgsnd for any destination cpu. */
@@ -225,10 +220,14 @@ void kvmhv_rm_send_ipi(int cpu)
                return;
        }
 
+       /* We should never reach this */
+       if (WARN_ON_ONCE(xive_enabled()))
+           return;
+
        /* Else poke the target with an IPI */
        xics_phys = paca[cpu].kvm_hstate.xics_phys;
        if (xics_phys)
-               rm_writeb(xics_phys + XICS_MFRR, IPI_PRIORITY);
+               __raw_rm_writeb(IPI_PRIORITY, xics_phys + XICS_MFRR);
        else
                opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY);
 }
@@ -387,6 +386,9 @@ long kvmppc_read_intr(void)
        long rc;
        bool again;
 
+       if (xive_enabled())
+               return 1;
+
        do {
                again = false;
                rc = kvmppc_read_one_intr(&again);
@@ -398,7 +400,7 @@ long kvmppc_read_intr(void)
 
 static long kvmppc_read_one_intr(bool *again)
 {
-       unsigned long xics_phys;
+       void __iomem *xics_phys;
        u32 h_xirr;
        __be32 xirr;
        u32 xisr;
@@ -416,7 +418,7 @@ static long kvmppc_read_one_intr(bool *again)
        if (!xics_phys)
                rc = opal_int_get_xirr(&xirr, false);
        else
-               xirr = _lwzcix(xics_phys + XICS_XIRR);
+               xirr = __raw_rm_readl(xics_phys + XICS_XIRR);
        if (rc < 0)
                return 1;
 
@@ -446,8 +448,8 @@ static long kvmppc_read_one_intr(bool *again)
        if (xisr == XICS_IPI) {
                rc = 0;
                if (xics_phys) {
-                       _stbcix(xics_phys + XICS_MFRR, 0xff);
-                       _stwcix(xics_phys + XICS_XIRR, xirr);
+                       __raw_rm_writeb(0xff, xics_phys + XICS_MFRR);
+                       __raw_rm_writel(xirr, xics_phys + XICS_XIRR);
                } else {
                        opal_int_set_mfrr(hard_smp_processor_id(), 0xff);
                        rc = opal_int_eoi(h_xirr);
@@ -472,7 +474,8 @@ static long kvmppc_read_one_intr(bool *again)
                         * we need to resend that IPI, bummer
                         */
                        if (xics_phys)
-                               _stbcix(xics_phys + XICS_MFRR, IPI_PRIORITY);
+                               __raw_rm_writeb(IPI_PRIORITY,
+                                               xics_phys + XICS_MFRR);
                        else
                                opal_int_set_mfrr(hard_smp_processor_id(),
                                                  IPI_PRIORITY);