powerpc/8xx: Rework CONFIG_PIN_TLB handling

[karo-tx-linux.git] / arch / powerpc / mm / 8xx_mmu.c

diff --git a/arch/powerpc/mm/8xx_mmu.c b/arch/powerpc/mm/8xx_mmu.c
index 949100577db536f389cbff597d21a5742e107715..0f0a83ed7a20b4934b56bfc7c7e1d81ed4d62b49 100644 (file)
--- a/arch/powerpc/mm/8xx_mmu.c
+++ b/arch/powerpc/mm/8xx_mmu.c
@@ -13,62 +13,111 @@
  */
 
 #include <linux/memblock.h>
+#include <asm/fixmap.h>
+#include <asm/code-patching.h>
 
 #include "mmu_decl.h"
 
+#define IMMR_SIZE (FIX_IMMR_SIZE << PAGE_SHIFT)
+
 extern int __map_without_ltlbs;
+
 /*
- * MMU_init_hw does the chip-specific initialization of the MMU hardware.
+ * Return PA for this VA if it is in IMMR area, or 0
  */
-void __init MMU_init_hw(void)
+phys_addr_t v_block_mapped(unsigned long va)
 {
-       /* Nothing to do for the time being but keep it similar to other PPC */
+       unsigned long p = PHYS_IMMR_BASE;
+
+       if (__map_without_ltlbs)
+               return 0;
+       if (va >= VIRT_IMMR_BASE && va < VIRT_IMMR_BASE + IMMR_SIZE)
+               return p + va - VIRT_IMMR_BASE;
+       return 0;
+}
+
+/*
+ * Return VA for a given PA or 0 if not mapped
+ */
+unsigned long p_block_mapped(phys_addr_t pa)
+{
+       unsigned long p = PHYS_IMMR_BASE;
+
+       if (__map_without_ltlbs)
+               return 0;
+       if (pa >= p && pa < p + IMMR_SIZE)
+               return VIRT_IMMR_BASE + pa - p;
+       return 0;
 }
 
-#define LARGE_PAGE_SIZE_4M     (1<<22)
 #define LARGE_PAGE_SIZE_8M     (1<<23)
-#define LARGE_PAGE_SIZE_64M    (1<<26)
 
-unsigned long __init mmu_mapin_ram(unsigned long top)
+/*
+ * MMU_init_hw does the chip-specific initialization of the MMU hardware.
+ */
+void __init MMU_init_hw(void)
 {
-       unsigned long v, s, mapped;
-       phys_addr_t p;
+       /* PIN up to the 3 first 8Mb after IMMR in DTLB table */
+#ifdef CONFIG_PIN_TLB
+       unsigned long ctr = mfspr(SPRN_MD_CTR) & 0xfe000000;
+       unsigned long flags = 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY;
+       int i;
+       unsigned long addr = 0;
+       unsigned long mem = total_lowmem;
+
+       for (i = 29; i < 32 && mem >= LARGE_PAGE_SIZE_8M; i++) {
+               mtspr(SPRN_MD_CTR, ctr | (i << 8));
+               mtspr(SPRN_MD_EPN, (unsigned long)__va(addr) | MD_EVALID);
+               mtspr(SPRN_MD_TWC, MD_PS8MEG | MD_SVALID);
+               mtspr(SPRN_MD_RPN, addr | flags | _PAGE_PRESENT);
+               addr += LARGE_PAGE_SIZE_8M;
+               mem -= LARGE_PAGE_SIZE_8M;
+       }
+#endif
+}
 
-       v = KERNELBASE;
-       p = 0;
-       s = top;
+static void mmu_mapin_immr(void)
+{
+       unsigned long p = PHYS_IMMR_BASE;
+       unsigned long v = VIRT_IMMR_BASE;
+       unsigned long f = pgprot_val(PAGE_KERNEL_NCG);
+       int offset;
 
-       if (__map_without_ltlbs)
-               return 0;
+       for (offset = 0; offset < IMMR_SIZE; offset += PAGE_SIZE)
+               map_page(v + offset, p + offset, f);
+}
 
-#ifdef CONFIG_PPC_4K_PAGES
-       while (s >= LARGE_PAGE_SIZE_8M) {
-               pmd_t *pmdp;
-               unsigned long val = p | MD_PS8MEG;
+/* Address of instructions to patch */
+#ifndef CONFIG_PIN_TLB
+extern unsigned int DTLBMiss_jmp;
+#endif
+extern unsigned int DTLBMiss_cmp, FixupDAR_cmp;
 
-               pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
-               *pmdp++ = __pmd(val);
-               *pmdp++ = __pmd(val + LARGE_PAGE_SIZE_4M);
+void mmu_patch_cmp_limit(unsigned int *addr, unsigned long mapped)
+{
+       unsigned int instr = *addr;
 
-               v += LARGE_PAGE_SIZE_8M;
-               p += LARGE_PAGE_SIZE_8M;
-               s -= LARGE_PAGE_SIZE_8M;
-       }
-#else /* CONFIG_PPC_16K_PAGES */
-       while (s >= LARGE_PAGE_SIZE_64M) {
-               pmd_t *pmdp;
-               unsigned long val = p | MD_PS8MEG;
+       instr &= 0xffff0000;
+       instr |= (unsigned long)__va(mapped) >> 16;
+       patch_instruction(addr, instr);
+}
 
-               pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
-               *pmdp++ = __pmd(val);
+unsigned long __init mmu_mapin_ram(unsigned long top)
+{
+       unsigned long mapped;
 
-               v += LARGE_PAGE_SIZE_64M;
-               p += LARGE_PAGE_SIZE_64M;
-               s -= LARGE_PAGE_SIZE_64M;
-       }
+       if (__map_without_ltlbs) {
+               mapped = 0;
+               mmu_mapin_immr();
+#ifndef CONFIG_PIN_TLB
+               patch_instruction(&DTLBMiss_jmp, PPC_INST_NOP);
 #endif
+       } else {
+               mapped = top & ~(LARGE_PAGE_SIZE_8M - 1);
+       }
 
-       mapped = top - s;
+       mmu_patch_cmp_limit(&DTLBMiss_cmp, mapped);
+       mmu_patch_cmp_limit(&FixupDAR_cmp, mapped);
 
        /* If the size of RAM is not an exact power of two, we may not
         * have covered RAM in its entirety with 8 MiB
@@ -77,7 +126,8 @@ unsigned long __init mmu_mapin_ram(unsigned long top)
         * coverage with normal-sized pages (or other reasons) do not
         * attempt to allocate outside the allowed range.
         */
-       memblock_set_current_limit(mapped);
+       if (mapped)
+               memblock_set_current_limit(mapped);
 
        return mapped;
 }
@@ -90,13 +140,8 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
         */
        BUG_ON(first_memblock_base != 0);
 
-#ifdef CONFIG_PIN_TLB
        /* 8xx can only access 24MB at the moment */
        memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01800000));
-#else
-       /* 8xx can only access 8MB at the moment */
-       memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
-#endif
 }
 
 /*