Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/fbdev...

[karo-tx-linux.git] / arch / powerpc / platforms / 85xx / p1022_ds.c

diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index a13d3cce413c7014453f05e3de670e3210ce3753..c01c7277888c1e3655fddd6be2dfe2da21705182 100644 (file)
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -130,6 +130,7 @@ static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
 static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
 {
        struct device_node *pixis_node;
+       void __iomem *pixis;
        u8 __iomem *brdcfg1;
 
        pixis_node = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis");
@@ -138,12 +139,12 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
                return;
        }
 
-       brdcfg1 = of_iomap(pixis_node, 0);
-       if (!brdcfg1) {
+       pixis = of_iomap(pixis_node, 0);
+       if (!pixis) {
                pr_err("p1022ds: could not map ngPIXIS registers\n");
                return;
        }
-       brdcfg1 += 9;   /* BRDCFG1 is at offset 9 in the ngPIXIS */
+       brdcfg1 = pixis + 9;    /* BRDCFG1 is at offset 9 in the ngPIXIS */
 
        switch (port) {
        case FSL_DIU_PORT_DVI:
@@ -161,6 +162,8 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
        default:
                pr_err("p1022ds: unsupported monitor port %i\n", port);
        }
+
+       iounmap(pixis);
 }
 
 /**
@@ -195,8 +198,13 @@ void p1022ds_set_pixel_clock(unsigned int pixclock)
        do_div(temp, pixclock);
        freq = temp;
 
-       /* pixclk is the ratio of the platform clock to the pixel clock */
+       /*
+        * 'pxclk' is the ratio of the platform clock to the pixel clock.
+        * This number is programmed into the CLKDVDR register, and the valid
+        * range of values is 2-255.
+        */
        pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
+       pxclk = clamp_t(u32, pxclk, 2, 255);
 
        /* Disable the pixel clock, and set it to non-inverted and no delay */
        clrbits32(&guts->clkdvdr,
@@ -204,6 +212,8 @@ void p1022ds_set_pixel_clock(unsigned int pixclock)
 
        /* Enable the clock and set the pxclk */
        setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+
+       iounmap(guts);
 }
 
 /**