arm: socfpga: Remove AV-specific parts from CV-SoCDK

[karo-tx-uboot.git] / board / altera / cyclone5-socdk / qts / sequencer_auto.h

diff --git a/board/altera/cyclone5-socdk/qts/sequencer_auto.h b/board/altera/cyclone5-socdk/qts/sequencer_auto.h
index 0c5d83bbdffcb88254b5b662c8e21ed1e82a4aed..d3c22515c5f7661d8cfa353ff4775acc1a260f19 100644 (file)
--- a/board/altera/cyclone5-socdk/qts/sequencer_auto.h
+++ b/board/altera/cyclone5-socdk/qts/sequencer_auto.h
@@ -19,29 +19,14 @@
 #define RW_MGR_MRS2 0x04
 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
 #define RW_MGR_MRS1 0x03
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define RW_MGR_IDLE_LOOP1 0x7A
-#else
 #define RW_MGR_IDLE_LOOP1 0x7C
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
 #define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
 #define RW_MGR_MRS3 0x05
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define RW_MGR_IDLE_LOOP2 0x79
-#else
 #define RW_MGR_IDLE_LOOP2 0x7B
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
 #define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
 #define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
 #define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define RW_MGR_RDIMM_CMD 0x78
-#else
 #define RW_MGR_RDIMM_CMD 0x7A
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
 #define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
@@ -54,12 +39,7 @@
 #define RW_MGR_GUARANTEED_WRITE 0x17
 #define RW_MGR_PRECHARGE_ALL 0x12
 #define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define RW_MGR_SGLE_READ 0x7C
-#else
 #define RW_MGR_SGLE_READ 0x7E
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
 #define RW_MGR_MRS0_USER_MIRR 0x0C
 #define RW_MGR_RETURN 0x01
 #define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35