pm9263 converted to at91 soc access

[karo-tx-uboot.git] / board / bf537-stamp / post-memory.c

diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c
index 60393505a283c9b755acb75a138dac1c94ea275a..4daea627ef56ea4c8462c1071f3cc5e3658f6041 100644 (file)
--- a/board/bf537-stamp/post-memory.c
+++ b/board/bf537-stamp/post-memory.c
@@ -1,12 +1,10 @@
 #include <common.h>
 #include <asm/io.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include <watchdog.h>
 
-#if CONFIG_POST & CFG_POST_MEMORY
+#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
 #define CLKIN 25000000
 #define PATTERN1 0x5A5A5A5A
 #define PATTERN2 0xAAAAAAAA
@@ -21,24 +19,24 @@ int post_init_sdram(int sclk);
 void post_init_uart(int sclk);
 
 const int pll[CCLK_NUM][SCLK_NUM][2] = {
-       {{20, 4}, {20, 5}, {20, 10}},   /* CCLK = 500M */
-       {{16, 4}, {16, 5}, {16, 8}},    /* CCLK = 400M */
-       {{8, 2}, {8, 4}, {8, 5}},       /* CCLK = 200M */
-       {{4, 1}, {4, 2}, {4, 4}}        /* CCLK = 100M */
+       { {20, 4}, {20, 5}, {20, 10} }, /* CCLK = 500M */
+       { {16, 4}, {16, 5}, {16, 8} },  /* CCLK = 400M */
+       { {8, 2}, {8, 4}, {8, 5} },     /* CCLK = 200M */
+       { {4, 1}, {4, 2}, {4, 4} }      /* CCLK = 100M */
 };
 const char *const log[CCLK_NUM][SCLK_NUM] = {
-       {"CCLK-500Mhz SCLK-125Mhz:    Writing...\0",
-        "CCLK-500Mhz SCLK-100Mhz:    Writing...\0",
-        "CCLK-500Mhz SCLK- 50Mhz:    Writing...\0",},
-       {"CCLK-400Mhz SCLK-100Mhz:    Writing...\0",
-        "CCLK-400Mhz SCLK- 80Mhz:    Writing...\0",
-        "CCLK-400Mhz SCLK- 50Mhz:    Writing...\0",},
-       {"CCLK-200Mhz SCLK-100Mhz:    Writing...\0",
-        "CCLK-200Mhz SCLK- 50Mhz:    Writing...\0",
-        "CCLK-200Mhz SCLK- 40Mhz:    Writing...\0",},
-       {"CCLK-100Mhz SCLK-100Mhz:    Writing...\0",
-        "CCLK-100Mhz SCLK- 50Mhz:    Writing...\0",
-        "CCLK-100Mhz SCLK- 25Mhz:    Writing...\0",},
+       {"CCLK-500MHz SCLK-125MHz:    Writing...\0",
+        "CCLK-500MHz SCLK-100MHz:    Writing...\0",
+        "CCLK-500MHz SCLK- 50MHz:    Writing...\0",},
+       {"CCLK-400MHz SCLK-100MHz:    Writing...\0",
+        "CCLK-400MHz SCLK- 80MHz:    Writing...\0",
+        "CCLK-400MHz SCLK- 50MHz:    Writing...\0",},
+       {"CCLK-200MHz SCLK-100MHz:    Writing...\0",
+        "CCLK-200MHz SCLK- 50MHz:    Writing...\0",
+        "CCLK-200MHz SCLK- 40MHz:    Writing...\0",},
+       {"CCLK-100MHz SCLK-100MHz:    Writing...\0",
+        "CCLK-100MHz SCLK- 50MHz:    Writing...\0",
+        "CCLK-100MHz SCLK- 25MHz:    Writing...\0",},
 };
 
 int memory_post_test(int flags)
@@ -71,10 +69,10 @@ int memory_post_test(int flags)
                        post_init_uart(sclk);
                        post_out_buff("\n\r\0");
                        post_out_buff(log[m][n]);
-                       for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4)
+                       for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4)
                                *(unsigned long *)addr = PATTERN1;
                        post_out_buff("Reading...\0");
-                       for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4) {
+                       for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) {
                                if ((*(unsigned long *)addr) != PATTERN1) {
                                        post_out_buff("Error\n\r\0");
                                        ret = 0;
@@ -104,30 +102,32 @@ void post_init_uart(int sclk)
 
        *pUART_GCTL = 0x00;
        *pUART_LCR = 0x83;
-       sync();
+       SSYNC();
        *pUART_DLL = (divisor & 0xFF);
-       sync();
+       SSYNC();
        *pUART_DLH = ((divisor >> 8) & 0xFF);
-       sync();
+       SSYNC();
        *pUART_LCR = 0x03;
-       sync();
+       SSYNC();
        *pUART_GCTL = 0x01;
-       sync();
+       SSYNC();
 }
 
 void post_out_buff(char *buff)
 {
 
        int i = 0;
-       for (i = 0; i < 0x80000; i++) ;
+       for (i = 0; i < 0x80000; i++)
+               ;
        i = 0;
        while ((buff[i] != '\0') && (i != 100)) {
                while (!(*pUART_LSR & 0x20)) ;
                *pUART_THR = buff[i];
-               sync();
+               SSYNC();
                i++;
        }
-       for (i = 0; i < 0x80000; i++) ;
+       for (i = 0; i < 0x80000; i++)
+               ;
 }
 
 /* Using sw10-PF5 as the hotkey */
@@ -141,7 +141,7 @@ int post_key_pressed(void)
        *pPORTF_FER &= ~PF5;
        *pPORTFIO_DIR &= ~PF5;
        *pPORTFIO_INEN |= PF5;
-       sync();
+       SSYNC();
 
        post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
        for (i = 0; i < KEY_LOOP; i++) {
@@ -150,9 +150,8 @@ int post_key_pressed(void)
                        value = 0;
                        goto key_pressed;
                }
-               if (value != 0) {
+               if (value != 0)
                        goto key_pressed;
-               }
                for (n = 0; n < KEY_DELAY; n++)
                        asm("nop");
        }
@@ -164,9 +163,8 @@ int post_key_pressed(void)
                        value = 0;
                        goto key_pressed;
                }
-               if (value != 0) {
+               if (value != 0)
                        goto key_pressed;
-               }
                for (n = 0; n < KEY_DELAY; n++)
                        asm("nop");
        }
@@ -178,9 +176,8 @@ int post_key_pressed(void)
                        value = 0;
                        goto key_pressed;
                }
-               if (value != 0) {
+               if (value != 0)
                        goto key_pressed;
-               }
                for (n = 0; n < KEY_DELAY; n++)
                        asm("nop");
        }
@@ -303,7 +300,7 @@ int post_init_sdram(int sclk)
            (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
             | PSS);
 
-       sync();
+       SSYNC();
 
        *pEBIU_SDGCTL |= 0x1000000;
        /* Set the SDRAM Refresh Rate control register based on SSCLK value */
@@ -314,9 +311,8 @@ int post_init_sdram(int sclk)
 
        /* SDRAM Memory Global Control Register */
        *pEBIU_SDGCTL = mem_SDGCTL;
-       sync();
+       SSYNC();
        return mem_SDRRC;
 }
 
-#endif                         /* CONFIG_POST & CFG_POST_MEMORY */
-#endif                         /* CONFIG_POST */
+#endif                         /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */