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Reworked FSL Book-E TLB macros to be more readable
[karo-tx-uboot.git] / board / freescale / mpc8544ds / init.S
diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
index 084d4b80d94a63421707a1cae2a3534225e60e62..544dc07c8dc4cf9424f00f2c9a7a096a9ab63dea 100644 (file)
--- a/board/freescale/mpc8544ds/init.S
+++ b/board/freescale/mpc8544ds/init.S
@@ -40,7 +40,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -71,10 +71,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB0         16K     Cacheable, guarded
@@ -87,33 +87,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
-
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -121,68 +113,63 @@ tlb1_entry:
         * 0xfc000000   64M     Covers FLASH at 0xFE800000 and 0xFF800000
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       1G      Non-cacheable, guarded
         * 0x80000000   1G      PCIE  8,9,a,b
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCIE_PHYS),
-               0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCIE_PHYS),
-               0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+       .long FSL_BOOKE_MAS2(CFG_PCIE_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCIE_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS),     0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       64M     Non-cacheable, guarded
         * 0xe000_0000  1M      CCSRBAR
         * 0xe100_0000  255M    PCI IO range
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 #ifdef CFG_LBC_CACHE_BASE
        /*
         * TLB 5:       64M     Cacheable, non-guarded
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #endif
        /*
         * TLB 6:       64M     Non-cacheable, guarded
         * 0xf8000000   64M     PIXIS 0xF8000000 - 0xFBFFFFFF
         */
-       .long TLB1_MAS0(1, 6, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 6, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 2:
        entry_end
 
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