/*
- * Copyright 2007,2009 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <i2c.h>
#include <ioports.h>
};
void local_bus_init(void);
-void sdram_init(void);
int board_early_init_f (void)
{
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
-
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
/*
* Initialize Local Bus
*/
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
- uint lbc_hz;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
if (clkdiv == 16) {
/*
* Initialize SDRAM memory on the Local Bus.
*/
-void
-sdram_init(void)
+void lbc_sdram_init(void)
{
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint lsdmr_common;
- puts(" SDRAM: ");
-
- print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+ puts("LBC SDRAM: ");
+ print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+ "\n ");
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CONFIG_SYS_OR2_PRELIM;
- asm("msync");
-
- lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
asm("msync");
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
-
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");
};
#endif
-static struct pci_controller pci1_hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_mpc8568mds_config_table,
-#endif
-};
+static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI */
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif /* CONFIG_PCIE1 */
-
/*
* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
*/
i2c_write(0x27, 0x3, 1, &val8, 1);
asm("eieio");
+ i2c_set_bus_num(orig_i2c_bus);
}
#ifdef CONFIG_PCI
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info[2];
+ int first_free_busno = 0;
+#ifdef CONFIG_PCI1
+ struct fsl_pci_info pci_info;
u32 devdisr, pordevsr, io_sel;
u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
- int first_free_busno = 0;
- int num = 0;
-
- int pcie_ep, pcie_configured;
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-#ifdef CONFIG_PCI1
pci_speed = 66666000;
pci_32 = 1;
pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info[num], 1);
- pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
- printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+ SET_STD_PCI_INFO(pci_info, 1);
+ set_next_law(pci_info.mem_phys,
+ law_size_bits(pci_info.mem_size), pci_info.law);
+ set_next_law(pci_info.io_phys,
+ law_size_bits(pci_info.io_size), pci_info.law);
+
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+ printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter",
- pci_info[num].regs);
+ pci_info.regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
+#ifndef CONFIG_PCI_PNP
+ pci1_hose.config_table = pci_mpc8568mds_config_table;
+#endif
+ first_free_busno = fsl_pci_init_port(&pci_info,
&pci1_hose, first_free_busno);
} else {
- printf (" PCI: disabled\n");
+ printf("PCI: disabled\n");
}
puts("\n");
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
-#ifdef CONFIG_PCIE1
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- SET_STD_PCIE_INFO(pci_info[num], 1);
- pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
-
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
- } else {
- printf (" PCIE1: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
+ fsl_pcie_init_board(first_free_busno);
}
#endif /* CONFIG_PCI */
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
+ FT_FSL_PCI_SETUP;
+
+ return 0;
}
#endif