powerpc/86xx: Rename PCI1/2 to PCIE1/2 on MPC8641HPCN & SBC8641

[karo-tx-uboot.git] / board / freescale / mpc8641hpcn / law.c

diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index bd357b86670e72973214dfccb10005d41d6d352d..8c8ce9585a316a8560d4f8d6dd6a422af0e93c41 100644 (file)
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -32,14 +32,14 @@
  *
  * 0x0000_0000     0x7fff_ffff     DDR                     2G
  * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0x8000_0000     0x9fff_ffff     PCIE1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCIE2 MEM                512M
  * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
  * 0x8000_0000     0x9fff_ffff     RapidIO                 512M
  * endif
  * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
- * 0xffc0_0000     0xffc0_ffff     PCI1 IO                 64K
- * 0xffc1_0000     0xffc1_ffff     PCI2 IO                 64K
+ * 0xffc0_0000     0xffc0_ffff     PCIE1 IO                 64K
+ * 0xffc1_0000     0xffc1_ffff     PCIE2 IO                 64K
  * 0xffe0_0000     0xffef_ffff     CCSRBAR                 1M
  * 0xffdf_0000     0xffe0_0000     PIXIS, CF               64K
  * 0xef80_0000     0xefff_ffff     FLASH (boot bank)       8M
@@ -54,10 +54,10 @@ struct law_entry law_table[] = {
        SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
 #endif
 #ifdef CONFIG_PCI
-       SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-       SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-       SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
-       SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
+       SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+       SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+       SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
+       SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
 #elif defined(CONFIG_RIO)
        SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif