Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

[karo-tx-uboot.git] / board / freescale / p1022ds / spl_minimal.c

diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c
index d150d95a2f0bc9bce9ef17399f5b5b720a15d8d7..8b343968437be445424cc94d06d71f7c20e9f115 100644 (file)
--- a/board/freescale/p1022ds/spl_minimal.c
+++ b/board/freescale/p1022ds/spl_minimal.c
@@ -12,51 +12,6 @@
 #include <asm/fsl_ddr_sdram.h>
 
 
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-void sdram_init(void)
-{
-       volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-
-       __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-       __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-       __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
-       __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
-       __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
-       __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
-       __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
-       __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
-
-       __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
-       __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
-       __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
-
-       __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
-       __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-       __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
-
-       __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
-       __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
-       __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-       __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
-
-       /* Set, but do not enable the memory */
-       __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN,
-                       &ddr->sdram_cfg);
-
-       in_be32(&ddr->sdram_cfg);
-       udelay(500);
-
-       /* Let the controller go */
-       out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-       in_be32(&ddr->sdram_cfg);
-
-       set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
-}
-
 const static u32 sysclk_tbl[] = {
        66666000, 7499900, 83332500, 8999900,
        99999000, 11111000, 12499800, 13333200
@@ -68,6 +23,10 @@ void board_init_f(ulong bootflag)
        u32 plat_ratio, sys_clk, bus_clk;
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+       set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+       set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
        /* for FPGA */
        set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
        set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
@@ -83,9 +42,6 @@ void board_init_f(ulong bootflag)
 
        puts("\nNAND boot... ");
 
-       /* Initialize the DDR3 */
-       sdram_init();
-
        /* copy code to RAM and jump to it - this should not return */
        /* NOTE - code has to be copied out of NAND buffer before
         * other blocks can be read.
@@ -96,6 +52,7 @@ void board_init_f(ulong bootflag)
 
 void board_init_r(gd_t *gd, ulong dest_addr)
 {
+       puts("\nSecond program loader running in sram...");
        nand_boot();
 }