Merge branch 'tx28-bugfix'

[karo-tx-uboot.git] / board / freescale / p2041rdb / cpld.c

diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c
index 8e1f46e79053cbcf5e06c90e03f71efb292a55db..34901aa3c904228c2e5c68835e4936bb06b2eec7 100644 (file)
--- a/board/freescale/p2041rdb/cpld.c
+++ b/board/freescale/p2041rdb/cpld.c
@@ -2,10 +2,7 @@
  * Copyright 2011 Freescale Semiconductor
  * Author: Mingkai Hu <Mingkai.hu@freescale.com>
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier:    GPL-2.0+
  *
  * This file provides support for the board-specific CPLD used on some Freescale
  * reference boards.
@@ -13,7 +10,6 @@
  * The following macros need to be defined:
  *
  * CPLD_BASE - The virtual address of the base of the CPLD register map
- *
  */
 
 #include <common.h>
@@ -53,7 +49,11 @@ void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
  */
 void __cpld_set_altbank(void)
 {
+       u8 reg5 = CPLD_READ(sw_ctl_on);
+
+       CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
        CPLD_WRITE(fbank_sel, 1);
+       CPLD_WRITE(system_rst, 1);
 }
 void cpld_set_altbank(void)
        __attribute__((weak, alias("__cpld_set_altbank")));
@@ -61,12 +61,12 @@ void cpld_set_altbank(void)
 /**
  * Set the boot bank to the default bank
  */
-void __cpld_clear_altbank(void)
+void __cpld_set_defbank(void)
 {
-       CPLD_WRITE(fbank_sel, 0);
+       CPLD_WRITE(system_rst_default, 1);
 }
-void cpld_clear_altbank(void)
-       __attribute__((weak, alias("__cpld_clear_altbank")));
+void cpld_set_defbank(void)
+       __attribute__((weak, alias("__cpld_set_defbank")));
 
 #ifdef DEBUG
 static void cpld_dump_regs(void)
@@ -75,7 +75,6 @@ static void cpld_dump_regs(void)
        printf("cpld_ver_sub    = 0x%02x\n", CPLD_READ(cpld_ver_sub));
        printf("pcba_ver        = 0x%02x\n", CPLD_READ(pcba_ver));
        printf("system_rst      = 0x%02x\n", CPLD_READ(system_rst));
-       printf("wd_cfg          = 0x%02x\n", CPLD_READ(wd_cfg));
        printf("sw_ctl_on       = 0x%02x\n", CPLD_READ(sw_ctl_on));
        printf("por_cfg         = 0x%02x\n", CPLD_READ(por_cfg));
        printf("switch_strobe   = 0x%02x\n", CPLD_READ(switch_strobe));
@@ -92,7 +91,6 @@ static void cpld_dump_regs(void)
 int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
        int rc = 0;
-       unsigned int i;
 
        if (argc <= 1)
                return cmd_usage(cmdtp);
@@ -101,16 +99,7 @@ int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
                if (strcmp(argv[2], "altbank") == 0)
                        cpld_set_altbank();
                else
-                       cpld_clear_altbank();
-
-               cpld_reset();
-       } else if (strcmp(argv[1], "watchdog") == 0) {
-               static char *period[8] = {"1ms", "10ms", "30ms", "disable",
-                       "100ms", "1s", "10s", "60s"};
-               for (i = 0; i < ARRAY_SIZE(period); i++) {
-                       if (strcmp(argv[2], period[i]) == 0)
-                               CPLD_WRITE(wd_cfg, i);
-               }
+                       cpld_set_defbank();
        } else if (strcmp(argv[1], "lane_mux") == 0) {
                u32 lane = simple_strtoul(argv[2], NULL, 16);
                u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
@@ -154,17 +143,15 @@ U_BOOT_CMD(
        "Reset the board or pin mulexing selection using the CPLD sequencer",
        "reset - hard reset to default bank\n"
        "cpld_cmd reset altbank - reset to alternate bank\n"
-       "cpld_cmd watchdog <watchdog_period> - set the watchdog period\n"
-       "       period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n"
        "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
-       "       lane 6: 0 -> slot1 (Default)\n"
-       "               1 -> SGMII\n"
-       "       lane a: 0 -> slot2 (Default)\n"
-       "               1 -> AURORA\n"
-       "       lane c: 0 -> slot2 (Default)\n"
-       "               1 -> SATA0\n"
-       "       lane d: 0 -> slot2 (Default)\n"
-       "               1 -> SATA1\n"
+       "       lane 6: 0 -> slot1\n"
+       "               1 -> SGMII (Default)\n"
+       "       lane a: 0 -> slot2\n"
+       "               1 -> AURORA (Default)\n"
+       "       lane c: 0 -> slot2\n"
+       "               1 -> SATA0 (Default)\n"
+       "       lane d: 0 -> slot2\n"
+       "               1 -> SATA1 (Default)\n"
 #ifdef DEBUG
        "cpld_cmd dump - display the CPLD registers\n"
 #endif