board: iocon: Support DisplayPort hardware

[karo-tx-uboot.git] / board / gdsys / common / osd.c

diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index c49cd9a619e152da94a354ae94afafe7e1298855..a839a4ec8e60b937bde3ff7e378bb2f21d4c9cfa 100644 (file)
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -58,45 +58,12 @@ unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
 int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
 #endif
 
-#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
-static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
-{
-       u16 val;
-
-       do {
-               FPGA_GET_REG(screen, extended_interrupt, &val);
-       } while (val & (1 << 12));
-
-       FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8));
-       FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1));
-}
-
-static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
-{
-       unsigned int ctr = 0;
-       u16 val;
-
-       do {
-               FPGA_GET_REG(screen, extended_interrupt, &val);
-       } while (val & (1 << 12));
-
-       FPGA_SET_REG(screen, extended_interrupt, 1 << 14);
-       FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg);
-       FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1));
-
-       FPGA_GET_REG(screen, extended_interrupt, &val);
-       while (!(val & (1 << 14))) {
-               udelay(100000);
-               if (ctr++ > 5) {
-                       printf("iic receive timeout\n");
-                       break;
-               }
-               FPGA_GET_REG(screen, extended_interrupt, &val);
-       }
+#ifdef CONFIG_SYS_ICS8N3QV01
+int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
+#endif
 
-       FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val);
-       return val >> 8;
-}
+#ifdef CONFIG_SYS_SIL1178
+int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
 #endif
 
 #ifdef CONFIG_SYS_MPC92469AC
@@ -153,7 +120,7 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout)
 
 #ifdef CONFIG_SYS_ICS8N3QV01
 
-static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index)
+static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
 {
        unsigned long long n;
        unsigned long long mint;
@@ -164,11 +131,11 @@ static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index)
        if (index > 3)
                return 0;
 
-       reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index);
-       reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index);
-       reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index);
-       reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index);
-       reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index);
+       reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
+       reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
+       reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
+       reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
+       reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);
 
        mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
        mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
@@ -216,7 +183,7 @@ static void ics8n3qv01_calc_parameters(unsigned int fout,
        *_n = n;
 }
 
-static void ics8n3qv01_set(unsigned screen, unsigned int fout)
+static void ics8n3qv01_set(unsigned int fout)
 {
        unsigned int n;
        unsigned int mint;
@@ -226,7 +193,7 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout)
        long long off_ppm;
        u8 reg0, reg4, reg8, reg12, reg18, reg20;
 
-       fout_calc = ics8n3qv01_get_fout_calc(screen, 1);
+       fout_calc = ics8n3qv01_get_fout_calc(1);
        off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
                  / ICS8N3QV01_F_DEFAULT_1;
        printf("       PLL is off by %lld ppm\n", off_ppm);
@@ -234,28 +201,28 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout)
                    / ICS8N3QV01_F_DEFAULT_1;
        ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
 
-       reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+       reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
        reg0 |= (mint & 0x1f) << 1;
        reg0 |= (mfrac >> 17) & 0x01;
-       fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
+       i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);
 
        reg4 = mfrac >> 9;
-       fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
+       i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);
 
        reg8 = mfrac >> 1;
-       fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
+       i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);
 
        reg12 = mfrac << 7;
        reg12 |= n & 0x7f;
-       fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
+       i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);
 
-       reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+       reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
        reg18 |= 0x20;
-       fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
+       i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);
 
-       reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+       reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
        reg20 |= mint & (1 << 5);
-       fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
+       i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
 }
 #endif
 
@@ -315,9 +282,7 @@ int osd_probe(unsigned screen)
        u16 version;
        u16 features;
        u8 value;
-#ifdef CONFIG_SYS_CH7301
        int old_bus = i2c_get_bus_num();
-#endif
 
        FPGA_GET_REG(0, osd.version, &version);
        FPGA_GET_REG(0, osd.features, &features);
@@ -345,7 +310,6 @@ int osd_probe(unsigned screen)
        i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
        i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
        i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
-       i2c_set_bus_num(old_bus);
 #endif
 
 #ifdef CONFIG_SYS_MPC92469AC
@@ -353,29 +317,31 @@ int osd_probe(unsigned screen)
 #endif
 
 #ifdef CONFIG_SYS_ICS8N3QV01
-       ics8n3qv01_set(screen, PIXCLK_640_480_60);
+       i2c_set_bus_num(ics8n3qv01_i2c[screen]);
+       ics8n3qv01_set(PIXCLK_640_480_60);
 #endif
 
 #ifdef CONFIG_SYS_SIL1178
-       value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
+       i2c_set_bus_num(sil1178_i2c[screen]);
+       value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02);
        if (value != 0x06) {
-               printf("       Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
+               printf("       Probing SIL1178, DEV_IDL %02x\n", value);
+               i2c_set_bus_num(old_bus);
                return -1;
        }
        /* magic initialization sequence adapted from datasheet */
-       fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
-       fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
-       fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
-       fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
-       fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
-       fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
-       fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
-       fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
-       fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
-       fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+       i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+       i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+       i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+       i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+       i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+       i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+       i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+       i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+       i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+       i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
 #endif
 
-       FPGA_SET_REG(screen, videocontrol, 0x0002);
        FPGA_SET_REG(screen, osd.control, 0x0049);
 
        FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
@@ -385,6 +351,8 @@ int osd_probe(unsigned screen)
        if (screen > max_osd_screen)
                max_osd_screen = screen;
 
+       i2c_set_bus_num(old_bus);
+
        return 0;
 }