+++ /dev/null
-#include <config.h>
-#include <configs/tx6q.h>
-#include <asm/arch/imx-regs.h>
-
-#define DEBUG_LED_BIT 20
-#define LED_GPIO_BASE GPIO2_BASE_ADDR
-#define LED_MUX_OFFSET 0x0ec
-#define LED_MUX_MODE 0x15
-
-#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
-
-#ifdef PHYS_SDRAM_2_SIZE
-#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
-#else
-#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
-#endif
-
-#if 1
-#define CPU_2_BE_32(l) \
- ((((l) << 24) & 0xFF000000) | \
- (((l) << 8) & 0x00FF0000) | \
- (((l) >> 8) & 0x0000FF00) | \
- (((l) >> 24) & 0x000000FF))
-#else
-#define CPU_2_BE_32(l) (l)
-#endif
-
-#define MXC_DCD_ITEM(addr, val) .word CPU_2_BE_32(addr), CPU_2_BE_32(val)
-
-#define CHECK_DCD_ADDR(a) ((((a) >= 0x00907000) && ((a) <= 0x00937FF0)) || \
- (((a) >= 0x020C4000) && ((a) < 0x020C8000)) || \
- (((a) >= 0x020C8000) && ((a) < 0x020C9000)) || \
- (((a) >= 0x020E0000) && ((a) < 0x020E4000)) || \
- (((a) >= 0x021B0000) && ((a) < 0x021B8000)) || \
- (((a) >= 0x08000000) && ((a) < 0x0FFF0000)) || \
- (((a) >= 0x10000000)))
-
-#define MXC_DCD_CMD_SZ_BYTE 1
-#define MXC_DCD_CMD_SZ_SHORT 2
-#define MXC_DCD_CMD_SZ_WORD 4
-#define MXC_DCD_CMD_FLAG_WRITE 0x0
-#define MXC_DCD_CMD_FLAG_CLR 0x1
-#define MXC_DCD_CMD_FLAG_SET 0x3
-#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
-#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
-#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
-
-#define MXC_DCD_CMD_WRT(type, flags, next) \
- .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
-
-#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
- .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
- CPU_2_BE_32(addr), CPU_2_BE_32(mask)
-
-#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
- .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
- CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
-
-#define MXC_DCD_CMD_NOP \
- .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
-
-#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
-#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
-
- .macro CK_VAL, name, clks, offs, max
- .iflt \clks - \offs
- .set \name, 0
- .else
- .ifle \clks - \offs - \max
- .set \name, \clks - \offs
- .endif
- .endif
- .endm
-
- .macro NS_VAL, name, ns, offs, max
- .iflt \ns - \offs
- .set \name, 0
- .else
- CK_VAL \name, NS_TO_CK(\ns), \offs, \max
- .endif
- .endm
-
- .macro CK_MAX, name, ck1, ck2, offs, max
- .ifgt \ck1 - \ck2
- CK_VAL \name, \ck1, \offs, \max
- .else
- CK_VAL \name, \ck2, \offs, \max
- .endif
- .endm
-
-#define MDMISC_DDR_TYPE_DDR3 0
-#define MDMISC_DDR_TYPE_LPDDR2 1
-#define MDMISC_DDR_TYPE_DDR2 2
-
-#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
-
-#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
-
-/* DDR3 SDRAM */
-#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
-#define BANK_ADDR_BITS 2
-#else
-#define BANK_ADDR_BITS 1
-#endif
-#define SDRAM_BURST_LENGTH 8
-#define RALAT 5
-#define WALAT 0
-#define BI_ON 1
-#define ADDR_MIRROR 1
-#define DDR_TYPE MDMISC_DDR_TYPE_DDR3
-
-/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
-/* MDCFG0 0x0c */
-NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
-CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
-CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
-CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
-NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
-CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */
-
-/* MDCFG1 0x10 */
-NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
-NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
-NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
-NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
-CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
-NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */
-
-/* MDCFG2 0x14 */
-CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
-CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
-CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
-CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
-
-/* MDOR 0x30 */
-CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
-#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
-#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
-
-/* MDOTC 0x08 */
-NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
-NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
-CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */
-CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */
-
-/* MDPDC 0x04 */
-CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7
-CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
-CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
-
-#define PRCT 0
-#define PWDT 5
-#define SLOW_PD 0
-#define BOTH_CS_PD 1
-
-#define MDPDC_VAL_0 ( \
- (tCKE << 16) | \
- (tCKSRX << 3) | \
- (tCKSRE << 0) \
- )
-
-#define MDPDC_VAL_1 (MDPDC_VAL_0 | \
- (PRCT << 28) | \
- (PRCT << 24) | \
- (PWDT << 12) | \
- (PWDT << 8) | \
- (BOTH_CS_PD << 6) | \
- (SLOW_PD << 7) \
- )
-
-#define ROW_ADDR_BITS 14
-#define COL_ADDR_BITS 10
-
- .iflt tWR - 7
- .set mrs_val, ((1 << 15) /* CON REQ */ | \
- (3 << 4) /* MRS command */ | \
- ((1 << 8) /* DLL Reset */ | \
- ((tWR + 1 - 4) << 9) | \
- (((tCL + 3) - 4) << 4)) << 16)
- .else
- .set mrs_val, ((1 << 15) /* CON REQ */ | \
- (3 << 4) /* MRS command */ | \
- ((1 << 8) /* DLL Reset */ | \
- (((tWR + 1) / 2) << 9) | \
- (((tCL + 3) - 4) << 4)) << 16)
- .endif
-#define MDSCR_MRS_VAL(cs) (mrs_val | ((cs) << 3))
-
-#define MDCFG0_VAL ( \
- (tRFC << 24) | \
- (tXS << 16) | \
- (tXP << 13) | \
- (tXPDLL << 9) | \
- (tFAW << 4) | \
- (tCL << 0)) \
-
-#define MDCFG1_VAL ( \
- (tRCD << 29) | \
- (tRP << 26) | \
- (tRC << 21) | \
- (tRAS << 16) | \
- (tRPA << 15) | \
- (tWR << 9) | \
- (tMRD << 5) | \
- (tCWL << 0)) \
-
-#define MDCFG2_VAL ( \
- (tDLLK << 16) | \
- (tRTP << 6) | \
- (tWTR << 3) | \
- (tRRD << 0))
-
-#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
-#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
- ((COL_ADDR_BITS - 9) << 20) | \
- (BURST_LEN << 19) | \
- (2 << 16) | /* SDRAM bus width */ \
- ((-1) << (32 - BANK_ADDR_BITS)))
-
-#define MDMISC_VAL ((ADDR_MIRROR << 19) | \
- (WALAT << 16) | \
- (BI_ON << 12) | \
- (0x3 << 9) | \
- (RALAT << 6) | \
- (DDR_TYPE << 3))
-
-#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
-
-#define MDOTC_VAL ((tAOFPD << 27) | \
- (tAONPD << 24) | \
- (tANPD << 20) | \
- (tAXPD << 16) | \
- (tODTLon << 12) | \
- (tODTLoff << 4))
-
-fcb_start:
- b _start
- .org 0x400
-ivt_header:
- .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
-app_start_addr:
- .long _start
- .long 0x0
-dcd_ptr:
- .long dcd_hdr
-boot_data_ptr:
- .word boot_data
-self_ptr:
- .word ivt_header
-app_code_csf:
- .word 0x0
- .word 0x0
-boot_data:
- .long fcb_start
-image_len:
- .long CONFIG_U_BOOT_IMG_SIZE
-plugin:
- .word 0
-ivt_end:
-#define DCD_VERSION 0x40
-
-#define CLKCTL_CCGR0 0x68
-#define CLKCTL_CCGR1 0x6c
-#define CLKCTL_CCGR2 0x70
-#define CLKCTL_CCGR3 0x74
-#define CLKCTL_CCGR4 0x78
-#define CLKCTL_CCGR5 0x7c
-#define CLKCTL_CCGR6 0x80
-#define CLKCTL_CCGR7 0x84
-#define CLKCTL_CMEOR 0x88
-
-#define DDR_SEL_VAL 3
-#define DSE_VAL 6
-#define ODT_VAL 2
-
-#define DDR_SEL_SHIFT 18
-#define DDR_MODE_SHIFT 17
-#define ODT_SHIFT 8
-#define DSE_SHIFT 3
-#define HYS_SHIFT 16
-#define PKE_SHIFT 12
-#define PUE_SHIFT 13
-#define PUS_SHIFT 14
-
-#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
-#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
-#define DSE_MASK (DSE_VAL << DSE_SHIFT)
-#define ODT_MASK (ODT_VAL << ODT_SHIFT)
-
-#define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
-#define SDQS_MASK DSE_MASK
-#define SDODT_MASK (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
-#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK)
-#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
-#define DDR_ADDR_MASK DDR_MODE_MASK
-#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK)
-
-dcd_hdr:
- .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
-dcd_start:
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
- /* RESET_OUT GPIO_7_12 */
- MXC_DCD_ITEM(0x020e024c, 0x00000005)
-#if 0
- /* STK5 LED GPIO */
- MXC_DCD_ITEM(0x020e00ec, (1 << 20))
-#endif
- MXC_DCD_ITEM(0x020c402c, 0x01e436c1) /* CSC2CDR default: 0x007236c1 */
- MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */
-
- /* enable all relevant clocks... */
- MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
- MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */
- MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
- MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */
- MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
- MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */
- MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
-
- /* IOMUX: */
- MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */
- /* UART1 pad config */
- MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */
- MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */
- MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */
- MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */
- MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */
- MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */
- /* NAND */
- MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */
- MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */
- MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
- MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
- MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
- MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */
- MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */
- MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */
- MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */
- MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */
- MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */
- MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */
- MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */
- MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */
- MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */
- /* ext. mem CS */
- MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
- /* DRAM_SDQS[0..7] */
- MXC_DCD_ITEM(0x020e05a8, SDQS_MASK)
- MXC_DCD_ITEM(0x020e05b0, SDQS_MASK)
- MXC_DCD_ITEM(0x020e0524, SDQS_MASK)
- MXC_DCD_ITEM(0x020e051c, SDQS_MASK)
- MXC_DCD_ITEM(0x020e0518, SDQS_MASK)
- MXC_DCD_ITEM(0x020e050c, SDQS_MASK)
- MXC_DCD_ITEM(0x020e05b8, SDQS_MASK)
- MXC_DCD_ITEM(0x020e05c0, SDQS_MASK)
- /* DRAM_DQM[0..7] */
- MXC_DCD_ITEM(0x020e05ac, DQM_MASK)
- MXC_DCD_ITEM(0x020e05b4, DQM_MASK)
- MXC_DCD_ITEM(0x020e0528, DQM_MASK)
- MXC_DCD_ITEM(0x020e0520, DQM_MASK)
- MXC_DCD_ITEM(0x020e0514, DQM_MASK)
- MXC_DCD_ITEM(0x020e0510, DQM_MASK)
- MXC_DCD_ITEM(0x020e05bc, DQM_MASK)
- MXC_DCD_ITEM(0x020e05c4, DQM_MASK)
- /* DRAM_A[0..15] */
- MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK)
- /* DRAM_CAS */
- MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK)
- /* DRAM_RAS */
- MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK)
- /* DRAM_SDCLK[0..1] */
- MXC_DCD_ITEM(0x020e0588, SDCLK_MASK)
- MXC_DCD_ITEM(0x020e0594, SDCLK_MASK)
- /* DRAM_RESET */
- MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK)
- /* DRAM_SDCKE[0..1] */
- MXC_DCD_ITEM(0x020e0590, SDCKE_MASK)
- MXC_DCD_ITEM(0x020e0598, SDCKE_MASK)
- /* DRAM_SDBA[0..2] */
- MXC_DCD_ITEM(0x020e0580, 0x00000000)
- MXC_DCD_ITEM(0x020e0584, 0x00000000)
- MXC_DCD_ITEM(0x020e058c, 0x00000000)
- /* DRAM_SDODT[0..1] */
- MXC_DCD_ITEM(0x020e059c, SDODT_MASK)
- MXC_DCD_ITEM(0x020e05a0, SDODT_MASK)
- /* DRAM_B[0..7]DS */
- MXC_DCD_ITEM(0x020e0784, DSE_MASK)
- MXC_DCD_ITEM(0x020e0788, DSE_MASK)
- MXC_DCD_ITEM(0x020e0794, DSE_MASK)
- MXC_DCD_ITEM(0x020e079c, DSE_MASK)
- MXC_DCD_ITEM(0x020e07a0, DSE_MASK)
- MXC_DCD_ITEM(0x020e07a4, DSE_MASK)
- MXC_DCD_ITEM(0x020e07a8, DSE_MASK)
- MXC_DCD_ITEM(0x020e0748, DSE_MASK)
- /* ADDDS */
- MXC_DCD_ITEM(0x020e074c, DSE_MASK)
- /* DDRMODE_CTL */
- MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK)
- /* DDRPKE */
- MXC_DCD_ITEM(0x020e0758, 0x00000000)
- /* DDRMODE */
- MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK)
- /* CTLDS */
- MXC_DCD_ITEM(0x020e078c, DSE_MASK)
- /* DDR_TYPE */
- MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK)
- /* DDRPK */
- MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT)
- /* DDRHYS */
- MXC_DCD_ITEM(0x020e0770, 0x00000000)
- /* TERM_CTL[0..7] */
-#if 0
- MXC_DCD_ITEM(0x020e0754, ODT_MASK)
- MXC_DCD_ITEM(0x020e075c, ODT_MASK)
- MXC_DCD_ITEM(0x020e0760, ODT_MASK)
- MXC_DCD_ITEM(0x020e0764, ODT_MASK)
- MXC_DCD_ITEM(0x020e076c, ODT_MASK)
- MXC_DCD_ITEM(0x020e0778, ODT_MASK)
- MXC_DCD_ITEM(0x020e077c, ODT_MASK)
- MXC_DCD_ITEM(0x020e0780, ODT_MASK)
-#endif
- /* SDRAM initialization */
-#if 1
- /* MPRDDQBY[0..7]DL */
- MXC_DCD_ITEM(0x021b081c, 0x33333333)
- MXC_DCD_ITEM(0x021b481c, 0x33333333)
- MXC_DCD_ITEM(0x021b0820, 0x33333333)
- MXC_DCD_ITEM(0x021b4820, 0x33333333)
- MXC_DCD_ITEM(0x021b0824, 0x33333333)
- MXC_DCD_ITEM(0x021b4824, 0x33333333)
- MXC_DCD_ITEM(0x021b0828, 0x33333333)
- MXC_DCD_ITEM(0x021b4828, 0x33333333)
-#endif
-MDMISC: /* MDMISC */
- MXC_DCD_ITEM(0x021b0018, MDMISC_VAL) ;@ 0x00081740
-MSDSCR: /* MSDSCR Conf Req */
- MXC_DCD_ITEM(0x021b001c, 0x00008000)
-con_ack:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
-MDCFG0: /* MDCFG0 */
- MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL) ;@ 0x555a7975
-MDCFG1: /* MDCFG1 */
- MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL) ;@ 0xff538e64
-MDCFG2: /* MDCFG2 */
- MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL) ;@ 0x01ff00db
-MDRWD: /* MDRWD */
- MXC_DCD_ITEM(0x021b002c, 0x000026d2)
-MDOR: /* MDOR */
- MXC_DCD_ITEM(0x021b0030, MDOR_VAL) ;@ 0x005b0e21
-MDOTC: /* MDOTC */
- MXC_DCD_ITEM(0x021b0008, MDOTC_VAL) ;@ 0x09444040
-MDPDC: /* MDPDC */
- MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1) ;@ 0x00025576
- MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0) ;@ 0x00025576
-MDASP: /* MDASP */
- MXC_DCD_ITEM(0x021b0040, 0x00000027)
-MDCTL: /* MDCTL */
- MXC_DCD_ITEM(0x021b0000, MDCTL_VAL);@ 0x831a0000
-ddr_calib:
- /* CS0 MRS: */
-MR2: /* MR2 */
- MXC_DCD_ITEM(0x021b001c, 0x04088032)
-MR3: /* MR3 */
- MXC_DCD_ITEM(0x021b001c, 0x00008033)
-MR1: /* MR1 */
- MXC_DCD_ITEM(0x021b001c, 0x00048031)
-MR0: /* MR0 */
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0)) ;@ 0x09408030
-#if BANK_ADDR_BITS > 1
- /* CS1 MRS: MR2 */
- MXC_DCD_ITEM(0x021b001c, 0x0408803a)
- MXC_DCD_ITEM(0x021b001c, 0x0000803b)
- MXC_DCD_ITEM(0x021b001c, 0x00408039)
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1)) ;@ 0x09408038
-#endif
-MDREF: /* MDREF */
- MXC_DCD_ITEM(0x021b0020, 0x00005800)
-MPODTCTRL: /* MPODTCTRL */
-#if 0
- MXC_DCD_ITEM(0x021b0818, 0x00011112) ;@ 0x00000007
- MXC_DCD_ITEM(0x021b4818, 0x00011112) ;@ 0x00000007
-#else
- MXC_DCD_ITEM(0x021b0818, 0x00000007)
- MXC_DCD_ITEM(0x021b4818, 0x00000007)
-#endif
- MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */
-
- /* ZQ calibration */
- MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
- MXC_DCD_ITEM(0x021b001c, 0x00008040) /* MRS: ZQ calibration */
-
- MXC_DCD_ITEM(0x021b0800, 0xa1390003)
-zq_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000)
-#if 1
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
- MXC_DCD_ITEM(0x021b001c, 0x00048033) /* MRS: select MPR */
- MXC_DCD_ITEM(0x021b001c, 0x00c08231) /* MRS: start write leveling */
-
- MXC_DCD_ITEM(0x021b001c, 0x00000000)
- MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */
- MXC_DCD_ITEM(0x021b4808, 0x00000001)
-wl_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00f00000)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00f00000)
-#endif
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
- MXC_DCD_ITEM(0x021b001c, 0x00048031) /* MRS: end write leveling */
- MXC_DCD_ITEM(0x021b001c, 0x00008033) /* MRS: select normal data path */
-
- /* DQS gating calibration */
- MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (3 << 16) | (3 << 9)) ;@ 0x00081740
-#if 1
- MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
- MXC_DCD_ITEM(0x021b001c, 0x00048033) /* MRS: select MPR */
-#if 1
- MXC_DCD_ITEM(0x021b0848, 0x47424140) /* DQ Delay default values */
- MXC_DCD_ITEM(0x021b4848, 0x41414047)
-#endif
- MXC_DCD_ITEM(0x021b083c, 0x90000000) /* reset RD fifo and start DQS calib. */
- MXC_DCD_ITEM(0x021b483c, 0x90000000)
-dqs_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x90000000)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x90000000)
-#endif
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
- MXC_DCD_ITEM(0x021b001c, 0x00008033) /* MRS: select normal data path */
-
- MXC_DCD_ITEM(0x021b001c, 0x00000000)
- MXC_DCD_ITEM(0x021b0018, MDMISC_VAL) ;@ 0x00081740
-
- /* Read delay calibration */
- MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
- MXC_DCD_ITEM(0x021b001c, 0x00048033) /* MRS: select MPR */
-#define DO_CALIB
-#ifdef DO_CALIB
- MXC_DCD_ITEM(0x021b0860, 0x00000010) /* MPRDDLHWCTL: HW_RD_DL_EN */
- MXC_DCD_ITEM(0x021b4860, 0x00000010)
-#endif
-rd_dl_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
- MXC_DCD_ITEM(0x021b001c, 0x00008033) /* MRS: select normal data path */
-
- /* Write Delay calibration */
- MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
- MXC_DCD_ITEM(0x021b001c, 0x00048033) /* MRS: select MPR */
-#ifdef DO_CALIB
- MXC_DCD_ITEM(0x021b0864, 0x00000010)
- MXC_DCD_ITEM(0x021b4864, 0x00000010)
-#endif
-wr_dl_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
- MXC_DCD_ITEM(0x021b001c, 0x00008033) /* MRS: select normal data path */
-
- /* MDSCR: Normal operation */
- MXC_DCD_ITEM(0x021b001c, 0x00000000)
-#if 0
- MXC_DCD_ITEM(0x021b0868, 0x00000000)
- MXC_DCD_ITEM(0x021b086c, 0x00000000)
- MXC_DCD_ITEM(0x021b4868, 0x00000000)
- MXC_DCD_ITEM(0x021b486c, 0x00000000)
-@ MXC_DCD_ITEM(0x021b0844, 0x1f251f21)
- MXC_DCD_ITEM(0x021b0898, 0x4ffa481a)
- MXC_DCD_ITEM(0x021b089c, 0x4ffa481a)
- MXC_DCD_ITEM(0x021b4898, 0x4ffa481a)
- MXC_DCD_ITEM(0x021b489c, 0x4ffa481a)
-#endif
-MAPSR: /* MAPSR */
- MXC_DCD_ITEM(0x021b0404, 0x00011006)
- MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1) ;@ 0x00025576
-#if 1
- MXC_DCD_ITEM(0x021b083c, 0x034b0350) /* DG_DL_ABS_OFFS[0..1] */
- MXC_DCD_ITEM(0x021b483c, 0x034b0350)
- MXC_DCD_ITEM(0x021b0840, 0x034c0359) /* DG_DL_ABS_OFFS[2..3] */
- MXC_DCD_ITEM(0x021b4840, 0x03650348)
-#endif
-#if 0
-bogus_ram_access:
- MXC_DCD_ITEM(0x12345678, 0x12345678)
-#endif
-dcd_end:
- .ifgt dcd_end - dcd_start - 1768
- DCD too large!
- .endif
projects / karo-tx-uboot.git / blobdiff