#include <asm/processor.h>
#include <pci.h>
#include <libfdt.h>
+#include <post.h>
#include "../common/common.h"
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* port pin dir open_drain assign */
-#if defined(CONFIG_KMETER1)
+#if defined(CONFIG_MPC8360)
/* MDIO */
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
-#else
+#elif !defined(CONFIG_MPC8309)
/* Local Bus */
{0, 16, 1, 0, 3}, /* LA00 */
{0, 17, 1, 0, 3}, /* LA01 */
setbits_8(&base->pgy_eth, 0x01);
/* enable the Unit LED (green) */
setbits_8(&base->oprth, WRL_BOOT);
+ /* enable Application Buffer */
+ setbits_8(&base->oprtl, OPRTL_XBUFENA);
#if defined(CONFIG_SUVD3)
/* configure UPMA for APP1 */
int last_stage_init(void)
{
+#if defined(CONFIG_KMCOGE5NE)
+ struct bfticu_iomap *base =
+ (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
+ u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+#endif
set_km_env();
return 0;
}
u32 ddr_size_log2;
out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
- out_be32(&im->ddr.csbnds[0].csbnds, CONFIG_SYS_DDR_CS0_BNDS);
+ out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
return 0;
}
#endif
+
+#if defined(CONFIG_POST)
+int post_hotkeys_pressed(void)
+{
+ int testpin = 0;
+ struct km_bec_fpga *base =
+ (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+ int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
+ testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
+ debug("post_hotkeys_pressed: %d\n", !testpin);
+ return testpin;
+}
+
+ulong post_word_load(void)
+{
+ void* addr = (ulong *) (CPM_POST_WORD_ADDR);
+ debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
+ return in_le32(addr);
+
+}
+void post_word_store(ulong value)
+{
+ void* addr = (ulong *) (CPM_POST_WORD_ADDR);
+ debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
+ out_le32(addr, value);
+}
+
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ *vstart = CONFIG_SYS_MEMTEST_START;
+ *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
+ debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
+
+ return 0;
+}
+#endif