#include <common.h>
#include <ns16550.h>
+#include <linux/compiler.h>
#include <asm/io.h>
-#include <asm/arch/tegra2.h>
-#include <asm/arch/sys_proto.h>
-
-#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/display.h>
+#include <asm/arch/emc.h>
+#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/uart.h>
+#include <asm/arch/pmu.h>
+#include <asm/arch/pwm.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/usb.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/uart.h>
+#include <asm/arch-tegra/warmboot.h>
+#include <spi.h>
+#include <i2c.h>
+#include "emc.h"
DECLARE_GLOBAL_DATA_PTR;
-const struct tegra2_sysinfo sysinfo = {
- CONFIG_TEGRA2_BOARD_STRING
+const struct tegra_sysinfo sysinfo = {
+ CONFIG_TEGRA_BOARD_STRING
};
+#ifndef CONFIG_SPL_BUILD
/*
* Routine: timer_init
* Description: init the timestamp and lastinc value
*/
int timer_init(void)
{
- reset_timer();
return 0;
}
+#endif
-/*
- * Routine: clock_init_uart
- * Description: init the PLL and clock for the UART(s)
- */
-static void clock_init_uart(void)
+void __pin_mux_usb(void)
{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- static int pllp_init_done;
- u32 reg;
-
- if (!pllp_init_done) {
- /* Override pllp setup for 216MHz operation. */
- reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
- reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
- writel(reg, &clkrst->crc_pllp_base);
-
- reg |= PLL_ENABLE;
- writel(reg, &clkrst->crc_pllp_base);
-
- reg &= ~PLL_BYPASS;
- writel(reg, &clkrst->crc_pllp_base);
-
- pllp_init_done++;
- }
-
- /* Now do the UART reset/clock enable */
-#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
- /* Assert Reset to UART */
- reg = readl(&clkrst->crc_rst_dev_l);
- reg |= SWR_UARTA_RST; /* SWR_UARTA_RST = 1 */
- writel(reg, &clkrst->crc_rst_dev_l);
-
- /* Enable clk to UART */
- reg = readl(&clkrst->crc_clk_out_enb_l);
- reg |= CLK_ENB_UARTA; /* CLK_ENB_UARTA = 1 */
- writel(reg, &clkrst->crc_clk_out_enb_l);
-
- /* Enable pllp_out0 to UART */
- reg = readl(&clkrst->crc_clk_src_uarta);
- reg &= 0x3FFFFFFF; /* UARTA_CLK_SRC = 00, PLLP_OUT0 */
- writel(reg, &clkrst->crc_clk_src_uarta);
-
- /* wait for 2us */
- udelay(2);
-
- /* De-assert reset to UART */
- reg = readl(&clkrst->crc_rst_dev_l);
- reg &= ~SWR_UARTA_RST; /* SWR_UARTA_RST = 0 */
- writel(reg, &clkrst->crc_rst_dev_l);
-#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
-#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
- /* Assert Reset to UART */
- reg = readl(&clkrst->crc_rst_dev_u);
- reg |= SWR_UARTD_RST; /* SWR_UARTD_RST = 1 */
- writel(reg, &clkrst->crc_rst_dev_u);
-
- /* Enable clk to UART */
- reg = readl(&clkrst->crc_clk_out_enb_u);
- reg |= CLK_ENB_UARTD; /* CLK_ENB_UARTD = 1 */
- writel(reg, &clkrst->crc_clk_out_enb_u);
-
- /* Enable pllp_out0 to UART */
- reg = readl(&clkrst->crc_clk_src_uartd);
- reg &= 0x3FFFFFFF; /* UARTD_CLK_SRC = 00, PLLP_OUT0 */
- writel(reg, &clkrst->crc_clk_src_uartd);
-
- /* wait for 2us */
- udelay(2);
-
- /* De-assert reset to UART */
- reg = readl(&clkrst->crc_rst_dev_u);
- reg &= ~SWR_UARTD_RST; /* SWR_UARTD_RST = 0 */
- writel(reg, &clkrst->crc_rst_dev_u);
-#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
}
-/*
- * Routine: pin_mux_uart
- * Description: setup the pin muxes/tristate values for the UART(s)
- */
-static void pin_mux_uart(void)
+void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb")));
+
+void __pin_mux_spi(void)
{
- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- u32 reg;
-
-#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
- reg = readl(&pmt->pmt_ctl_c);
- reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
- writel(reg, &pmt->pmt_ctl_c);
-
- reg = readl(&pmt->pmt_tri_a);
- reg &= ~Z_IRRX; /* Z_IRRX = normal (0) */
- reg &= ~Z_IRTX; /* Z_IRTX = normal (0) */
- writel(reg, &pmt->pmt_tri_a);
-#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
-#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
- reg = readl(&pmt->pmt_ctl_b);
- reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */
- writel(reg, &pmt->pmt_ctl_b);
-
- reg = readl(&pmt->pmt_tri_a);
- reg &= ~Z_GMC; /* Z_GMC = normal (0) */
- writel(reg, &pmt->pmt_tri_a);
-#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
}
-/*
- * Routine: clock_init
- * Description: Do individual peripheral clock reset/enables
- */
-void clock_init(void)
+void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
+
+void __gpio_early_init_uart(void)
{
- clock_init_uart();
}
+void gpio_early_init_uart(void)
+__attribute__((weak, alias("__gpio_early_init_uart")));
+
+void __pin_mux_nand(void)
+{
+ funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
+}
+
+void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
+
/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
+ * Routine: power_det_init
+ * Description: turn off power detects
*/
-void pinmux_init(void)
+static void power_det_init(void)
{
- pin_mux_uart();
+#if defined(CONFIG_TEGRA20)
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ /* turn off power detects */
+ writel(0, &pmc->pmc_pwr_det_latch);
+ writel(0, &pmc->pmc_pwr_det);
+#endif
}
/*
*/
int board_init(void)
{
+ __maybe_unused int err;
+
+ /* Do clocks and UART first so that printf() works */
+ clock_init();
+ clock_verify();
+
+#ifdef CONFIG_SPI_UART_SWITCH
+ gpio_config_uart();
+#endif
+#ifdef CONFIG_TEGRA_SPI
+ pin_mux_spi();
+ spi_init();
+#endif
+#ifdef CONFIG_PWM_TEGRA
+ if (pwm_init(gd->fdt_blob))
+ debug("%s: Failed to init pwm\n", __func__);
+#endif
+#ifdef CONFIG_LCD
+ tegra_lcd_check_next_stage(gd->fdt_blob, 0);
+#endif
/* boot param addr */
gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
- /* board id for Linux */
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
- /* Initialize peripheral clocks */
- clock_init();
+ power_det_init();
+
+#ifdef CONFIG_TEGRA_I2C
+#ifndef CONFIG_SYS_I2C_INIT_BOARD
+#error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards"
+#endif
+ i2c_init_board();
+# ifdef CONFIG_TEGRA_PMU
+ if (pmu_set_nominal())
+ debug("Failed to select nominal voltages\n");
+# ifdef CONFIG_TEGRA_CLOCK_SCALING
+ err = board_emc_init();
+ if (err)
+ debug("Memory controller init failed: %d\n", err);
+# endif
+# endif /* CONFIG_TEGRA_PMU */
+#endif /* CONFIG_TEGRA_I2C */
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+ pin_mux_usb();
+ board_usb_init(gd->fdt_blob);
+#endif
+#ifdef CONFIG_LCD
+ tegra_lcd_check_next_stage(gd->fdt_blob, 0);
+#endif
+
+#ifdef CONFIG_TEGRA_NAND
+ pin_mux_nand();
+#endif
+
+#ifdef CONFIG_TEGRA_LP0
+ /* save Sdram params to PMC 2, 4, and 24 for WB0 */
+ warmboot_save_sdram_params();
+
+ /* prepare the WB code to LP0 location */
+ warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
+#endif
+
+ return 0;
+}
- /* Initialize periph pinmuxes */
- pinmux_init();
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+static void __gpio_early_init(void)
+{
+}
+
+void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
+
+int board_early_init_f(void)
+{
+ board_init_uart_f();
+
+ /* Initialize periph GPIOs */
+ gpio_early_init();
+ gpio_early_init_uart();
+#ifdef CONFIG_LCD
+ tegra_lcd_early_init(gd->fdt_blob);
+#endif
return 0;
}
+#endif /* EARLY_INIT */
+int board_late_init(void)
+{
+#ifdef CONFIG_LCD
+ /* Make sure we finish initing the LCD */
+ tegra_lcd_check_next_stage(gd->fdt_blob, 1);
+#endif
+ return 0;
+}
projects / karo-tx-uboot.git / blobdiff