* Dave Ellis, SIXNET, dge@sixnetio.com.
* Based on code by:
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * and other contributors to U-Boot. See file CREDITS for list
- * of people who contributed to this project.
+ * and other contributors to U-Boot.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
# include <status_led.h>
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-#endif
+DECLARE_GLOBAL_DATA_PTR;
#define ORMASK(size) ((-size) & OR_AM_MSK)
{
#if defined(CONFIG_STATUS_LED)
# if defined(STATUS_LED_BOOT)
- if (status == 15) {
+ if (status == BOOTSTAGE_ID_RUN_OS) {
/* ready to transfer to kernel, make sure LED is proper state */
status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
}
/* ------------------------------------------------------------------------- */
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#if defined(CONFIG_CMD_PCMCIA)
#error "SXNI855T has no PCMCIA port"
-#endif /* CFG_CMD_PCMCIA */
+#endif
/* ------------------------------------------------------------------------- */
#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */
#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */
#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */
-#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG)) /* FPGA port */
+#define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG)) /* FPGA port */
int board_postclk_init (void)
{
# include "fpgadata.c"
};
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
#define porta (immap->im_ioport.iop_padat)
const unsigned char* pdata;
/* ------------------------------------------------------------------------- */
/* base address for SRAM, assume 32-bit port, valid */
-#define NVRAM_BR_VALUE (CFG_SRAM_BASE | BR_PS_32 | BR_V)
+#define NVRAM_BR_VALUE (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V)
/* up to 64MB - will be adjusted for actual size */
-#define NVRAM_OR_PRELIM (ORMASK(CFG_SRAM_SIZE) \
+#define NVRAM_OR_PRELIM (ORMASK(CONFIG_SYS_SRAM_SIZE) \
| OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
/*
* Miscellaneous platform dependent initializations after running in RAM.
int misc_init_r (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- char* s;
- char* e;
- int reg;
bd_t *bd = gd->bd;
+ uchar enetaddr[6];
memctl->memc_or2 = NVRAM_OR_PRELIM;
memctl->memc_br2 = NVRAM_BR_VALUE;
/* Is there any SRAM? Is it 16 or 32 bits wide? */
/* First look for 32-bit SRAM */
- bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+ bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
if (bd->bi_sramsize == 0) {
/* no 32-bit SRAM, but there could be 16-bit SRAM since
* Try again with a 16-bit bus.
*/
memctl->memc_br2 |= BR_PS_16;
- bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+ bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
}
if (bd->bi_sramsize == 0) {
else {
/* adjust or2 for actual size of SRAM */
memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
- bd->bi_sramstart = CFG_SRAM_BASE;
+ bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10);
}
* is present it gets a unique address, otherwise it
* shares the FEC address.
*/
- s = getenv("eth1addr");
- if (s == NULL)
- s = getenv("ethaddr");
- for (reg=0; reg<6; ++reg) {
- bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0;
- if (s)
- s = (*e) ? e+1 : e;
+ if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
+ eth_getenv_enetaddr("ethaddr", enetaddr);
+ eth_setenv_enetaddr("eth1addr", enetaddr);
}
return (0);
}
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
void nand_init(void)
{
- unsigned long totlen = nand_probe(CFG_DFLASH_BASE);
+ unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
/* ------------------------------------------------------------------------- */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
uint size_sdram = 0;
uint size_sdram9 = 0;
projects / karo-tx-uboot.git / blobdiff