board/T1040qds: Fix lane-to-slot mapping for SerDes protocol 0x89

[karo-tx-uboot.git] / board / socrates / law.c

diff --git a/board/socrates/law.c b/board/socrates/law.c
index 5f4b8ca4f90c375bc07e287641026cfebe25e6c7..449a030820423db8f2f7d1d397f618e1c2ba8eac 100644 (file)
--- a/board/socrates/law.c
+++ b/board/socrates/law.c
@@ -7,23 +7,7 @@
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -33,13 +17,13 @@
 /*
  * LAW(Local Access Window) configuration:
  *
- * 0x0000_0000    0x7fff_ffff     DDR                     2G
+ * 0x0000_0000    0x2fff_ffff     DDR                     512M
  * 0x8000_0000    0x9fff_ffff     PCI1 MEM                512M
- * 0xc000_0000    0xdfff_ffff     RapidIO                 512M
- * 0xe000_0000    0xe000_ffff     CCSR                    1M
+ * 0xc000_0000    0xc00f_ffff     FPGA                    1M
+ * 0xc800_0000    0xcbff_ffff     LIME                    64M
+ * 0xe000_0000    0xe00f_ffff     CCSR                    1M (mapped by CCSRBAR)
  * 0xe200_0000    0xe2ff_ffff     PCI1 IO                 16M
- * 0xf800_0000    0xf80f_ffff     BCSR                    1M
- * 0xfe00_0000    0xffff_ffff     FLASH (boot bank)       32M
+ * 0xfc00_0000    0xffff_ffff     FLASH                   64M
  *
  * Notes:
  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
@@ -47,11 +31,14 @@
  */
 
 struct law_entry law_table[] = {
-       SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-       SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-       SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-       SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+       SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+       SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+       SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+#if defined(CONFIG_SYS_FPGA_BASE)
+       SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+       SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);