karo: fdt: fix inverted pixelclock polarity

[karo-tx-uboot.git] / board / sunxi / gmac.c

diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 4e4615e12f654fed06c8200ce5061e1ba76e2493..4e222d88c0d3a9d543ace1f1c17665394f8f25cb 100644 (file)
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -13,31 +13,24 @@ int sunxi_gmac_initialize(bd_t *bis)
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
        /* Set up clock gating */
-#ifndef CONFIG_MACH_SUN6I
-       setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
-#else
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
        setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
+#else
+       setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
 #endif
 
        /* Set MII clock */
 #ifdef CONFIG_RGMII
        setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
                CCM_GMAC_CTRL_GPIT_RGMII);
+       setbits_le32(&ccm->gmac_clk_cfg,
+                    CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
 #else
        setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
                CCM_GMAC_CTRL_GPIT_MII);
 #endif
 
-       /*
-        * In order for the gmac nic to work reliable on the Bananapi, we
-        * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain"
-        * of the GMAC clk register to 3.
-        */
-#if defined CONFIG_TARGET_BANANAPI || defined CONFIG_TARGET_BANANAPRO
-       setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
-#endif
-
 #ifndef CONFIG_MACH_SUN6I
        /* Configure pin mux settings for GMAC */
        for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
@@ -46,52 +39,56 @@ int sunxi_gmac_initialize(bd_t *bis)
                if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
                        continue;
 #endif
-               sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
+               sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
                sunxi_gpio_set_drv(pin, 3);
        }
 #elif defined CONFIG_RGMII
        /* Configure sun6i RGMII mode pin mux settings */
        for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
-               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
                sunxi_gpio_set_drv(pin, 3);
        }
        for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
-               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
                sunxi_gpio_set_drv(pin, 3);
        }
        for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
-               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
                sunxi_gpio_set_drv(pin, 3);
        }
        for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
-               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
                sunxi_gpio_set_drv(pin, 3);
        }
 #elif defined CONFIG_GMII
        /* Configure sun6i GMII mode pin mux settings */
        for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
-               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
                sunxi_gpio_set_drv(pin, 2);
        }
 #else
        /* Configure sun6i MII mode pin mux settings */
        for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
-               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
        for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
-               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
        for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
-               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
        for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
-               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
        for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
-               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
 #endif
 
-#ifdef CONFIG_RGMII
+#ifdef CONFIG_DM_ETH
+       return 0;
+#else
+# ifdef CONFIG_RGMII
        return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
-#elif defined CONFIG_GMII
+# elif defined CONFIG_GMII
        return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
-#else
+# else
        return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
+# endif
 #endif
 }