* Patches by Thomas Viehweger, 16 Mar 2004:

[karo-tx-uboot.git] / common / miiphyutil.c

diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index af8c7c7a310695dc45d0c7d9a805a353b97b5769..f6436cf2452583555f0a96be0969dbd8727a6a89 100644 (file)
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -51,7 +51,7 @@ int miiphy_info (unsigned char addr,
 
        if (miiphy_read (addr, PHY_PHYIDR2, &tmp) != 0) {
 #ifdef DEBUG
-               printf ("PHY ID register 2 read failed\n");
+               puts ("PHY ID register 2 read failed\n");
 #endif
                return (-1);
        }
@@ -67,7 +67,7 @@ int miiphy_info (unsigned char addr,
 
        if (miiphy_read (addr, PHY_PHYIDR1, &tmp) != 0) {
 #ifdef DEBUG
-               printf ("PHY ID register 1 read failed\n");
+               puts ("PHY ID register 1 read failed\n");
 #endif
                return (-1);
        }
@@ -95,11 +95,13 @@ int miiphy_reset (unsigned char addr)
 
        if (miiphy_write (addr, PHY_BMCR, 0x8000) != 0) {
 #ifdef DEBUG
-               printf ("PHY reset failed\n");
+               puts ("PHY reset failed\n");
 #endif
                return (-1);
        }
-
+#ifdef CONFIG_PHY_RESET_DELAY
+       udelay (CONFIG_PHY_RESET_DELAY);        /* Intel LXT971A needs this */
+#endif
        /*
         * Poll the control register for the reset bit to go to 0 (it is
         * auto-clearing).  This should happen within 0.5 seconds per the
@@ -110,7 +112,7 @@ int miiphy_reset (unsigned char addr)
        while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
                if (miiphy_read (addr, PHY_BMCR, &reg) != 0) {
 #     ifdef DEBUG
-                       printf ("PHY status read failed\n");
+                       puts ("PHY status read failed\n");
 #     endif
                        return (-1);
                }
@@ -118,7 +120,7 @@ int miiphy_reset (unsigned char addr)
        if ((reg & 0x8000) == 0) {
                return (0);
        } else {
-               printf ("PHY reset timed out\n");
+               puts ("PHY reset timed out\n");
                return (-1);
        }
        return (0);
@@ -133,11 +135,20 @@ int miiphy_speed (unsigned char addr)
 {
        unsigned short reg;
 
+       if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
+               printf ("PHY 1000BT Status read failed\n");
+       } else {
+               if (reg != 0xFFFF) {
+                       if ((reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) !=0) {
+                               return (_1000BASET);
+                       }
+               }
+       }
+
        if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
-               printf ("PHY speed1 read failed, assuming 10bT\n");
+               puts ("PHY speed1 read failed, assuming 10bT\n");
                return (_10BASET);
        }
-
        if ((reg & PHY_ANLPAR_100) != 0) {
                return (_100BASET);
        } else {
@@ -154,8 +165,22 @@ int miiphy_duplex (unsigned char addr)
 {
        unsigned short reg;
 
+
+       if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
+               printf ("PHY 1000BT Status read failed\n");
+       } else {
+               if ( (reg != 0xFFFF) &&
+                    (reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) ) {
+                       if ((reg & PHY_1000BTSR_1000FD) !=0) {
+                               return (FULL);
+                       } else {
+                               return (HALF);
+                       }
+               }
+       }
+
        if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
-               printf ("PHY duplex read failed, assuming half duplex\n");
+               puts ("PHY duplex read failed, assuming half duplex\n");
                return (HALF);
        }
 
@@ -176,7 +201,7 @@ int miiphy_link (unsigned char addr)
        unsigned short reg;
 
        if (miiphy_read (addr, PHY_BMSR, &reg)) {
-               printf ("PHY_BMSR read failed, assuming no link\n");
+               puts ("PHY_BMSR read failed, assuming no link\n");
                return (0);
        }