ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)

[karo-tx-uboot.git] / cpu / ppc4xx / cpu.c

diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 53da5a3e76af445120cb7b46215d52db8eba2b67..8e6bc84db038e4141f079b345e24c16dc5d689a5 100644 (file)
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -47,6 +47,9 @@ void board_reset(void);
 
 #if defined(CONFIG_440)
 #define FREQ_EBC               (sys_info.freqEPB)
+#elif defined(CONFIG_405EZ)
+#define FREQ_EBC               ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \
+                                sys_info.pllExtBusDiv)
 #else
 #define FREQ_EBC               (sys_info.freqPLB / sys_info.pllExtBusDiv)
 #endif
@@ -88,14 +91,18 @@ int pci_arbiter_enabled(void)
        return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
 #endif
 
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
        unsigned long val;
 
-       mfsdr(sdr_sdstp1, val);
-       return (val & SDR0_SDSTP1_PAE_MASK);
+       mfsdr(sdr_xcr, val);
+       return (val & 0x80000000);
+#endif
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+       unsigned long val;
+
+       mfsdr(sdr_pci0, val);
+       return (val & 0x80000000);
 #endif
 }
 #endif
@@ -118,6 +125,7 @@ int i2c_bootrom_enabled(void)
        return (val & SDR0_SDCS_SDD);
 #endif
 }
+#endif
 
 #if defined(CONFIG_440GX)
 #define SDR0_PINSTP_SHIFT      29
@@ -171,16 +179,37 @@ static char *bootstrap_str[] = {
 };
 #endif
 
+#if defined(CONFIG_405EZ)
+#define SDR0_PINSTP_SHIFT      28
+static char *bootstrap_str[] = {
+       "EBC (8 bits)",
+       "SPI (fast)",
+       "NAND (512 page, 4 addr cycle)",
+       "I2C (Addr 0x50)",
+       "EBC (32 bits)",
+       "I2C (Addr 0x50)",
+       "NAND (2K page, 5 addr cycle)",
+       "I2C (Addr 0x50)",
+       "EBC (16 bits)",
+       "Reserved",
+       "NAND (2K page, 4 addr cycle)",
+       "I2C (Addr 0x50)",
+       "NAND (512 page, 3 addr cycle)",
+       "I2C (Addr 0x50)",
+       "SPI (slow)",
+       "I2C (Addr 0x50)",
+};
+#endif
+
 #if defined(SDR0_PINSTP_SHIFT)
 static int bootstrap_option(void)
 {
        unsigned long val;
 
-       mfsdr(sdr_pinstp, val);
-       return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT);
+       mfsdr(SDR_PINSTP, val);
+       return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
 }
 #endif /* SDR0_PINSTP_SHIFT */
-#endif
 
 
 #if defined(CONFIG_440)
@@ -205,7 +234,8 @@ int checkcpu (void)
 
        puts("AMCC PowerPC 4");
 
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+    defined(CONFIG_405EP) || defined(CONFIG_405EZ)
        puts("05");
 #endif
 #if defined(CONFIG_440)
@@ -253,6 +283,10 @@ int checkcpu (void)
                puts("EP Rev. B");
                break;
 
+       case PVR_405EZ_RA:
+               puts("EZ Rev. A");
+               break;
+
 #if defined(CONFIG_440)
        case PVR_440GP_RB:
                puts("GP Rev. B");
@@ -312,25 +346,29 @@ int checkcpu (void)
 #endif /* CONFIG_440GR */
 #endif /* CONFIG_440 */
 
-       case PVR_440EPX1_RA:
+#ifdef CONFIG_440EPX
+       case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
                puts("EPx Rev. A");
                strcpy(addstr, "Security/Kasumi support");
                break;
 
-       case PVR_440EPX2_RA:
+       case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
                puts("EPx Rev. A");
                strcpy(addstr, "No Security/Kasumi support");
                break;
+#endif /* CONFIG_440EPX */
 
-       case PVR_440GRX1_RA:
+#ifdef CONFIG_440GRX
+       case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
                puts("GRx Rev. A");
                strcpy(addstr, "Security/Kasumi support");
                break;
 
-       case PVR_440GRX2_RA:
+       case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
                puts("GRx Rev. A");
                strcpy(addstr, "No Security/Kasumi support");
                break;
+#endif /* CONFIG_440GRX */
 
        case PVR_440SP_6_RAB:
                puts("SP Rev. A/B");
@@ -378,20 +416,20 @@ int checkcpu (void)
        }
 
        printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
-              sys_info.freqPLB / 1000000,
-              sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
-              FREQ_EBC / 1000000);
+               sys_info.freqPLB / 1000000,
+               get_OPB_freq() / 1000000,
+               FREQ_EBC / 1000000);
 
        if (addstr[0] != 0)
                printf("       %s\n", addstr);
 
 #if defined(I2C_BOOTROM)
        printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
+#endif /* I2C_BOOTROM */
 #if defined(SDR0_PINSTP_SHIFT)
        printf ("       Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
        printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
 #endif /* SDR0_PINSTP_SHIFT */
-#endif /* I2C_BOOTROM */
 
 #if defined(CONFIG_PCI)
        printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
@@ -410,7 +448,7 @@ int checkcpu (void)
        putc('\n');
 #endif
 
-#if defined(CONFIG_405EP)
+#if defined(CONFIG_405EP) || defined(CONFIG_405EZ)
        printf ("       16 kB I-Cache 16 kB D-Cache");
 #elif defined(CONFIG_440)
        printf ("       32 kB I-Cache 32 kB D-Cache");
@@ -439,7 +477,7 @@ int ppc440spe_revB() {
        unsigned int pvr;
 
        pvr = get_pvr();
-       if (pvr == PVR_440SPe_RB)
+       if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
                return 1;
        else
                return 0;